From 92dd8ee8f5a456b9b27fc162e3ffbe84e0592333 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 20 Sep 2024 17:46:27 -0400
Subject: [PATCH] Fix timing mode not exiting on empty events (#5472).

---
 Changes                           |  1 +
 src/V3EmitCMain.cpp               |  4 +++-
 test_regress/t/t_timing_finish.py | 18 ++++++++++++++++++
 test_regress/t/t_timing_finish.v  | 13 +++++++++++++
 4 files changed, 35 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_timing_finish.py
 create mode 100644 test_regress/t/t_timing_finish.v

diff --git a/Changes b/Changes
index d65967f93..4e2a92845 100644
--- a/Changes
+++ b/Changes
@@ -55,6 +55,7 @@ Verilator 5.029 devel
 * Fix foreach colliding index names (#5444). [Arkadiusz Kozdra, Antmicro Ltd.]
 * Fix fault on defparam with UNSUPPORTED ignored (#5450). [Luiza de Melo]
 * Fix class reference with pin that is a class reference (#5454).
+* Fix timing mode not exiting on empty events (#5472).
 
 
 Verilator 5.028 2024-08-21
diff --git a/src/V3EmitCMain.cpp b/src/V3EmitCMain.cpp
index ac31e7f32..6112f2f2c 100644
--- a/src/V3EmitCMain.cpp
+++ b/src/V3EmitCMain.cpp
@@ -85,8 +85,10 @@ private:
         puts(/**/ "// Evaluate model\n");
         puts(/**/ "topp->eval();\n");
         puts(/**/ "// Advance time\n");
-        if (v3Global.rootp()->delaySchedulerp()) {
+        if (v3Global.rootp()->delaySchedulerp() || v3Global.opt.timing()) {
             puts("if (!topp->eventsPending()) break;\n");
+        }
+        if (v3Global.rootp()->delaySchedulerp()) {
             puts("contextp->time(topp->nextTimeSlot());\n");
         } else {
             puts("contextp->timeInc(1);\n");
diff --git a/test_regress/t/t_timing_finish.py b/test_regress/t/t_timing_finish.py
new file mode 100755
index 000000000..671072f97
--- /dev/null
+++ b/test_regress/t/t_timing_finish.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=['--binary'])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_timing_finish.v b/test_regress/t/t_timing_finish.v
new file mode 100644
index 000000000..4e035a9b1
--- /dev/null
+++ b/test_regress/t/t_timing_finish.v
@@ -0,0 +1,13 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+program t;
+   initial begin
+      #1;
+      $write("*-* All Finished *-*\n");
+      // No $finish
+   end
+endprogram