diff --git a/Changes b/Changes
index b0a38c614..de8932d59 100644
--- a/Changes
+++ b/Changes
@@ -4,6 +4,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 * Verilator 3.923 devel
 
+****  Report interface ports connected to wrong interface, bug1294. [Todd Strader]
+
 ****  Fix parsing "output signed" in V2K port list, msg2540. [James Jung]
 
 
diff --git a/src/V3Param.cpp b/src/V3Param.cpp
index 12f27b179..adbbcc93e 100644
--- a/src/V3Param.cpp
+++ b/src/V3Param.cpp
@@ -652,6 +652,14 @@ void ParamVisitor::visitCell(AstCell* nodep) {
 			longname += "_" + paramSmallName(srcModp, pinp->modVarp()) + paramValueNumber(pinIrefp);
 			any_overrides = true;
 			ifaceRefRefs.push_back(make_pair(portIrefp,pinIrefp));
+                        if (portIrefp->ifacep() != pinIrefp->ifacep()
+                            // Might be different only due to param cloning, so check names too
+                            && portIrefp->ifaceName() != pinIrefp->ifaceName()) {
+                            pinp->v3error("Port '"<<pinp->prettyName()<<"' expects '"
+                                          <<AstNode::prettyName(portIrefp->ifaceName())
+                                          <<"' interface but pin connects '"
+                                          <<AstNode::prettyName(pinIrefp->ifaceName())<<"' interface");
+                        }
 		    }
 		}
 	    }
diff --git a/test_regress/t/t_interface_wrong_bad.pl b/test_regress/t/t_interface_wrong_bad.pl
new file mode 100755
index 000000000..c773241b2
--- /dev/null
+++ b/test_regress/t/t_interface_wrong_bad.pl
@@ -0,0 +1,17 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    fails=>1,
+    expect =>
+q{%Error: t/t_interface_wrong_bad.v:\d+: Port 'foo_port' expects 'foo_intf' interface but pin connects 'bar_intf' interface},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_interface_wrong_bad.v b/test_regress/t/t_interface_wrong_bad.v
new file mode 100644
index 000000000..233b9a656
--- /dev/null
+++ b/test_regress/t/t_interface_wrong_bad.v
@@ -0,0 +1,39 @@
+// DESCRIPTION: Verilator: Using the wrong kind of interface in a portmap
+// should cause an error
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2018 by Todd Strader.
+
+interface foo_intf;
+   logic [7:0] a;
+endinterface
+
+interface bar_intf;
+   logic [7:0] a;
+endinterface
+
+module foo_mod (foo_intf foo_port);
+//  initial begin
+//      $display("a = %0d", foo_port.a);
+//  end
+endmodule
+
+module t (/*AUTOARG*/);
+
+   foo_intf foo ();
+   bar_intf bar ();
+
+//   assign foo.a = 8'd1;
+//   assign bar.a = 8'd2;
+
+   foo_mod
+   foo_mod (
+      .foo_port (bar)
+   );
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule