diff --git a/Changes b/Changes index c795078c2..cc192ba53 100644 --- a/Changes +++ b/Changes @@ -11,6 +11,11 @@ contributors that suggested a given feature are shown in []. Thanks! Verilator 5.023 devel ========================== +**Major:** + +* Support 1800-2023 keywords. + + **Minor:** * Add warning on 'TOP'-named modules (#4935). [Yanglin Xun] diff --git a/bin/verilator b/bin/verilator index 64a41305c..d38058f77 100755 --- a/bin/verilator +++ b/bin/verilator @@ -308,6 +308,7 @@ detailed descriptions of these arguments. +1800-2009ext+ Use SystemVerilog 2009 with file extension +1800-2012ext+ Use SystemVerilog 2012 with file extension +1800-2017ext+ Use SystemVerilog 2017 with file extension + +1800-2023ext+ Use SystemVerilog 2023 with file extension --assert Enable all assertions --assert-case Enable unique/unique0/priority case related checks --autoflush Flush streams after all $displays @@ -437,7 +438,7 @@ detailed descriptions of these arguments. --no-stop-fail Do not call $stop when assertion fails --structs-packed Convert all unpacked structures to packed structures -sv Enable SystemVerilog parsing - +systemverilogext+ Synonym for +1800-2017ext+ + +systemverilogext+ Synonym for +1800-2023ext+ --threads Enable multithreading --threads-dpi Enable multithreaded DPI --threads-max-mtasks Tune maximum mtask partitioning diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index 6a9b6dae8..44c86b7b2 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -51,6 +51,8 @@ Summary: .. option:: +1800-2017ext+ +.. option:: +1800-2023ext+ + Specifies the language standard to be used with a specific filename extension, . @@ -349,7 +351,7 @@ Summary: Select the language used by default when first processing each Verilog file. The language value must be "VAMS", "1364-1995", "1364-2001", "1364-2001-noconfig", "1364-2005", "1800-2005", - "1800-2009", "1800-2012", "1800-2017", or "1800+VAMS". + "1800-2009", "1800-2012", "1800-2017", "1800-2023", or "1800+VAMS". Any language associated with a particular file extension (see the various +*\ ext+ options) will be used in preference to the @@ -362,7 +364,7 @@ Summary: ``+ext+`` options should be used. If no language is specified, either by this option or ``+ext+`` - options, then the latest SystemVerilog language (IEEE 1800-2017) is + options, then the latest SystemVerilog language (IEEE 1800-2023) is used. .. option:: +define+= @@ -1299,12 +1301,12 @@ Summary: .. option:: -sv Specifies SystemVerilog language features should be enabled; equivalent - to :vlopt:`--language 1800-2017 <--language>`. This option is selected + to :vlopt:`--language 1800-2023 <--language>`. This option is selected by default; it exists for compatibility with other simulators. .. option:: +systemverilogext+ - A synonym for :vlopt:`+1800-2017ext+\`. + A synonym for :vlopt:`+1800-2023ext+\`. .. option:: --threads diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst index c8575bec1..6301c84d3 100644 --- a/docs/guide/extensions.rst +++ b/docs/guide/extensions.rst @@ -36,8 +36,7 @@ or "`ifdef`"'s may break other tools. .. option:: """ [string] """ A triple-quoted block specifies a string that may include newlines and - single quotes. This extension is experimental and may be removed - without deprecation. + single quotes. This extension was standardized in IEEE 1800-2023. .. option:: $c([string], ...); @@ -619,4 +618,4 @@ or "`ifdef`"'s may break other tools. symbols. Also, the data represents the C++ stack; the SystemVerilog functions/tasks involved may be renamed and/or inlined before becoming the C++ functions that may be visible in the stack trace. This - extension is experimental and may be removed without deprecation. + extension was standardized in IEEE 1800-2023. diff --git a/docs/guide/languages.rst b/docs/guide/languages.rst index 201f37fec..d5c598cc3 100644 --- a/docs/guide/languages.rst +++ b/docs/guide/languages.rst @@ -62,6 +62,13 @@ Verilator supports the 2017 "for" loop constructs and several cleanups IEEE made in 1800-2017. +SystemVerilog 2023 (IEEE 1800-2023) Support +------------------------------------------- + +Verilator supports some of the 2023 improvements, including triple-quoted +string blocks that may include newlines and single quotes. + + Verilog AMS Support ------------------- diff --git a/docs/guide/overview.rst b/docs/guide/overview.rst index 002ef8b45..95cf9cb17 100644 --- a/docs/guide/overview.rst +++ b/docs/guide/overview.rst @@ -50,6 +50,6 @@ The best place to get started is to try the :ref:`Examples`. .. [#] SystemVerilog is defined by the `Institute of Electrical and Electronics Engineers (IEEE) Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language`, Standard - 1800, released in 2005, 2009, 2012, and 2017. The Verilator - documentation uses the shorthand e.g., "IEEE 1800-2017", to refer to - the, e.g., 2017 version of this standard. + 1800, released in 2005, 2009, 2012, 2017, and 2023. The Verilator + documentation uses the shorthand e.g., "IEEE 1800-2023", to refer to + the, e.g., 2023 version of this standard. diff --git a/src/V3LangCode.h b/src/V3LangCode.h index 6403bec25..0de1b5678 100644 --- a/src/V3LangCode.h +++ b/src/V3LangCode.h @@ -39,18 +39,21 @@ public: L1800_2009, L1800_2012, L1800_2017, + L1800_2023, // ***Add new elements below also*** _ENUM_END }; const char* ascii() const { - const char* const names[] = {// These must match the `begin_keywords values. - " ERROR", "1364-1995", "1364-2001", "1364-2005", - "1800-2005", "1800-2009", "1800-2012", "1800-2017"}; + const char* const names[] + = {// These must match the `begin_keywords values + " ERROR", "1364-1995", "1364-2001", "1364-2005", "1800-2005", + "1800-2009", "1800-2012", "1800-2017", "1800-2023"}; return names[m_e]; } - static V3LangCode mostRecent() VL_MT_SAFE { return V3LangCode{L1800_2017}; } + static V3LangCode mostRecent() VL_MT_SAFE { return V3LangCode{L1800_2023}; } bool systemVerilog() const { - return m_e == L1800_2005 || m_e == L1800_2009 || m_e == L1800_2012 || m_e == L1800_2017; + return m_e == L1800_2005 || m_e == L1800_2009 || m_e == L1800_2012 || m_e == L1800_2017 + || m_e == L1800_2023; } bool legal() const { return m_e != L_ERROR; } // diff --git a/src/V3Options.cpp b/src/V3Options.cpp index f0daaef6c..332227c61 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -1102,6 +1102,8 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, [this](const char* optp) { addLangExt(optp, V3LangCode::L1800_2012); }); DECL_OPTION("+1800-2017ext+", CbPartialMatch, [this](const char* optp) { addLangExt(optp, V3LangCode::L1800_2017); }); + DECL_OPTION("+1800-2023ext+", CbPartialMatch, + [this](const char* optp) { addLangExt(optp, V3LangCode::L1800_2023); }); // Minus options DECL_OPTION("-assert", OnOff, &m_assert); @@ -1446,7 +1448,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, DECL_OPTION("-std", OnOff, &m_std); DECL_OPTION("-stop-fail", OnOff, &m_stopFail); DECL_OPTION("-structs-packed", OnOff, &m_structsPacked); - DECL_OPTION("-sv", CbCall, [this]() { m_defaultLanguage = V3LangCode::L1800_2017; }); + DECL_OPTION("-sv", CbCall, [this]() { m_defaultLanguage = V3LangCode::L1800_2023; }); DECL_OPTION("-threads-coarsen", OnOff, &m_threadsCoarsen).undocumented(); // Debug DECL_OPTION("-no-threads", CbCall, [this, fl]() { diff --git a/src/verilog.l b/src/verilog.l index 1f67441c8..5e9c82281 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -27,7 +27,7 @@ #include "V3ParseBison.h" // Generated by bison #include "V3ParseImp.h" // Defines YYTYPE; before including bison header -#define STATE_VERILOG_RECENT S17 // State name for most recent Verilog Version +#define STATE_VERILOG_RECENT S23 // State name for most recent Verilog Version #define PARSEP V3ParseImp::parsep() @@ -78,7 +78,7 @@ static double lexParseDouble(FileLine* fl, const char* textp, size_t length) { %a 15000 %o 25000 -%s V95 V01NC V01C V05 S05 S09 S12 S17 +%s V95 V01NC V01C V05 S05 S09 S12 S17 S23 %s ATTRMODE QQQ STRING TABLE %s VA5 SAX VLT %s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR @@ -159,7 +159,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /************************************************************************/ /* Verilog 1995 */ -{ +{ {ws} { FL_FWD; FL_BRK; } /* otherwise ignore white-space */ {crnl} { FL_FWD; FL_BRK; } /* Count line numbers */ /* Extensions to Verilog set, some specified by PSL */ @@ -410,7 +410,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* Verilog 2001 */ -{ +{ /* System Tasks */ "$signed" { FL; return yD_SIGNED; } "$unsigned" { FL; return yD_UNSIGNED; } @@ -430,7 +430,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* Verilog 2001 Config */ -{ +{ /* Generic unsupported keywords */ "cell" { ERROR_RSVD_WORD("Verilog 2001-config"); } "config" { ERROR_RSVD_WORD("Verilog 2001-config"); } @@ -447,7 +447,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* Verilog 2005 */ -{ +{ /* System Tasks */ "$clog2" { FL; return yD_CLOG2; } /* Keywords */ @@ -455,7 +455,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* System Verilog 2005 */ -{ +{ /* System Tasks */ "$bits" { FL; return yD_BITS; } "$changed" { FL; return yD_CHANGED; } @@ -590,7 +590,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* SystemVerilog 2009 */ -{ +{ /* Keywords */ "accept_on" { FL; return yACCEPT_ON; } "checker" { FL; return yCHECKER; } @@ -617,7 +617,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* System Verilog 2012 */ -{ +{ /* Keywords */ "implements" { FL; return yIMPLEMENTS; } "interconnect" { FL; return yINTERCONNECT; } @@ -629,7 +629,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /* No new keywords */ /* Default PLI rule */ -{ +{ "$"[a-zA-Z0-9_$]+ { const string str (yytext, yyleng); yylval.strp = PARSEP->newString(AstNode::encodeName(str)); FL; return yaD_PLI; @@ -734,7 +734,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /* Meta comments */ /* Converted from //{cmt}verilator ...{cmt} by preprocessor */ -{ +{ "/*verilator"{ws}*"*/" { FL_FWD; FL_BRK; } /* Ignore empty comments, may be `endif // verilator */ "/*verilator clock_enable*/" { FL; return yVL_CLOCK_ENABLE; } "/*verilator clocker*/" { FL; return yVL_CLOCKER; } @@ -786,7 +786,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /************************************************************************/ /* Single character operator thingies */ -{ +{ "{" { FL; return yytext[0]; } "}" { FL; return yytext[0]; } "!" { FL; return yytext[0]; } @@ -820,7 +820,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /* Operators and multi-character symbols */ /* Verilog 1995 Operators */ -{ +{ "&&" { FL; return yP_ANDAND; } "||" { FL; return yP_OROR; } "<=" { FL; return yP_LTE; } @@ -842,7 +842,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* Verilog 2001 Operators */ -{ +{ "<<<" { FL; return yP_SLEFT; } ">>>" { FL; return yP_SSRIGHT; } "**" { FL; return yP_POW; } @@ -855,7 +855,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* SystemVerilog Operators */ -{ +{ "'" { FL; return yP_TICK; } "'{" { FL; return yP_TICKBRA; } "==?" { FL; return yP_WILDEQUAL; } @@ -892,12 +892,12 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} } /* SystemVerilog 2009 Operators */ -{ +{ "<->" { FL; return yP_LTMINUSGT; } } /* Identifiers and numbers */ -{ +{ {escid} { FL; yylval.strp = PARSEP->newString (AstNode::encodeName(std::string{yytext+1})); // +1 to skip the backslash return yaID__LEX; @@ -991,7 +991,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /************************************************************************/ /* Attributes */ /* Note simulators vary in support for "(* /_*something*_/ foo*)" where _ doesn't exist */ -{ +{ "(*"({ws}|{crnl})*({id}|{escid}) { yymore(); yy_push_state(ATTRMODE); } /* Doesn't match (*), but (* attr_spec */ } @@ -1011,7 +1011,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /* Common for all SYSC header states */ /* OPTIMIZE: we return one per line, make it one for the entire block */ /* If add to this list also add to V3LanguageWords.h */ -{ +{ "`accelerate" { FL_FWD; FL_BRK; } // Verilog-XL compatibility "`autoexpand_vectornets" { FL_FWD; FL_BRK; } // Verilog-XL compatibility "`celldefine" { FL_FWD; PARSEP->lexFileline()->celldefineOn(true); FL_BRK; } @@ -1067,6 +1067,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "`begin_keywords"[ \t]*\"1800-2009\" { FL_FWD; yy_push_state(S09); PARSEP->lexPushKeywords(YY_START); FL_BRK; } "`begin_keywords"[ \t]*\"1800-2012\" { FL_FWD; yy_push_state(S12); PARSEP->lexPushKeywords(YY_START); FL_BRK; } "`begin_keywords"[ \t]*\"1800-2017\" { FL_FWD; yy_push_state(S17); PARSEP->lexPushKeywords(YY_START); FL_BRK; } + "`begin_keywords"[ \t]*\"1800-2023\" { FL_FWD; yy_push_state(S23); PARSEP->lexPushKeywords(YY_START); FL_BRK; } "`begin_keywords"[ \t]*\"1800[+]VAMS\" { FL_FWD; yy_push_state(SAX); PARSEP->lexPushKeywords(YY_START); FL_BRK; } /*Latest SV*/ "`end_keywords" { FL; if (!PARSEP->lexPopKeywords()) { @@ -1108,7 +1109,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /************************************************************************/ /* Default rules - leave last */ -{ +{ "`"[a-zA-Z_0-9]+ { FL; V3ParseImp::lexErrorPreprocDirective(yylval.fl, yytext); FL_BRK; } "//"[^\n]* { FL_FWD; FL_BRK; } /* throw away single line comments */ . { FL; return yytext[0]; } /* return single char ops. */ diff --git a/test_regress/t/t_constraint_xml.out b/test_regress/t/t_constraint_xml.out index fd9e5c556..a72fc51eb 100644 --- a/test_regress/t/t_constraint_xml.out +++ b/test_regress/t/t_constraint_xml.out @@ -2,13 +2,13 @@ - - - - + + + + - + diff --git a/test_regress/t/t_preproc_kwd.v b/test_regress/t/t_preproc_kwd.v index bee3632e0..e9318dc75 100644 --- a/test_regress/t/t_preproc_kwd.v +++ b/test_regress/t/t_preproc_kwd.v @@ -18,6 +18,7 @@ module t (/*AUTOARG*/ s09 s09 (); s12 s12 (); s17 s17 (); + s23 s23 (); a23 a23 (); @@ -83,6 +84,14 @@ module s17; endmodule `end_keywords +`begin_keywords "1800-2023" +module s23; + final begin + $write("*-* All Finished *-*\n"); + end +endmodule +`end_keywords + `begin_keywords "VAMS-2.3" module a23; real foo; initial foo = sqrt(2.0); diff --git a/test_regress/t/t_var_port_xml.out b/test_regress/t/t_var_port_xml.out index abbbdb652..2620f3e61 100644 --- a/test_regress/t/t_var_port_xml.out +++ b/test_regress/t/t_var_port_xml.out @@ -2,13 +2,13 @@ - - - - + + + + - + diff --git a/test_regress/t/t_xml_begin_hier.out b/test_regress/t/t_xml_begin_hier.out index 0a71073d6..32276460d 100644 --- a/test_regress/t/t_xml_begin_hier.out +++ b/test_regress/t/t_xml_begin_hier.out @@ -2,13 +2,13 @@ - - - - + + + + - + diff --git a/test_regress/t/t_xml_debugcheck.out b/test_regress/t/t_xml_debugcheck.out index 44ae98bf4..6e1c8d97c 100644 --- a/test_regress/t/t_xml_debugcheck.out +++ b/test_regress/t/t_xml_debugcheck.out @@ -2,13 +2,13 @@ - - - - + + + + - + diff --git a/test_regress/t/t_xml_first.out b/test_regress/t/t_xml_first.out index 1056865dc..1b4130a9b 100644 --- a/test_regress/t/t_xml_first.out +++ b/test_regress/t/t_xml_first.out @@ -2,13 +2,13 @@ - - - - + + + + - + diff --git a/test_regress/t/t_xml_flat.out b/test_regress/t/t_xml_flat.out index 454eb60d2..42fd9a767 100644 --- a/test_regress/t/t_xml_flat.out +++ b/test_regress/t/t_xml_flat.out @@ -2,13 +2,13 @@ - - - - + + + + - + diff --git a/test_regress/t/t_xml_flat_no_inline_mod.out b/test_regress/t/t_xml_flat_no_inline_mod.out index da52f5e15..a753f1603 100644 --- a/test_regress/t/t_xml_flat_no_inline_mod.out +++ b/test_regress/t/t_xml_flat_no_inline_mod.out @@ -2,13 +2,13 @@ - - - - + + + + - + diff --git a/test_regress/t/t_xml_flat_pub_mod.out b/test_regress/t/t_xml_flat_pub_mod.out index 55f3600d4..79db75794 100644 --- a/test_regress/t/t_xml_flat_pub_mod.out +++ b/test_regress/t/t_xml_flat_pub_mod.out @@ -2,13 +2,13 @@ - - - - + + + + - + diff --git a/test_regress/t/t_xml_flat_vlvbound.out b/test_regress/t/t_xml_flat_vlvbound.out index 006f33f89..2cba16ed9 100644 --- a/test_regress/t/t_xml_flat_vlvbound.out +++ b/test_regress/t/t_xml_flat_vlvbound.out @@ -2,13 +2,13 @@ - - - - + + + + - + diff --git a/test_regress/t/t_xml_output.out b/test_regress/t/t_xml_output.out index c2ca4faf4..b42d1ae68 100644 --- a/test_regress/t/t_xml_output.out +++ b/test_regress/t/t_xml_output.out @@ -2,13 +2,13 @@ - - - - + + + + - + diff --git a/test_regress/t/t_xml_tag.out b/test_regress/t/t_xml_tag.out index fecebf1ba..cfc91c506 100644 --- a/test_regress/t/t_xml_tag.out +++ b/test_regress/t/t_xml_tag.out @@ -2,13 +2,13 @@ - - - - + + + + - +