From 902ba752a3179ecb35d2146c71573fc58aba7f66 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 31 May 2019 21:05:50 -0400 Subject: [PATCH] Move many unsupported errors from lex to parser so can --bbox-unsup ignore them. --- src/verilog.l | 63 +++++++++--------- src/verilog.y | 173 +++++++++++++++++++++++++++++++++----------------- 2 files changed, 149 insertions(+), 87 deletions(-) diff --git a/src/verilog.l b/src/verilog.l index 61dee69af..d966a6212 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -298,16 +298,24 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "endspecify" { FL; return yENDSPECIFY; } "endtable" { yyerrorf("Syntax error: ENDTABLE outside of TABLE"); } "endtask" { FL; return yENDTASK; } + "event" { FL; return yEVENT; } "for" { FL; return yFOR; } + "force" { FL; return yFORCE; } "foreach" { FL; return yFOREACH; } "forever" { FL; return yFOREVER; } + "fork" { FL; return yFORK; } "function" { FL; return yFUNCTION; } + "highz0" { FL; return ygenSTRENGTH; } + "highz1" { FL; return ygenSTRENGTH; } "if" { FL; return yIF; } "initial" { FL; return yINITIAL; } "inout" { FL; return yINOUT; } "input" { FL; return yINPUT; } "integer" { FL; return yINTEGER; } + "join" { FL; return yJOIN; } + "large" { FL; return ygenSTRENGTH; } "macromodule" { FL; return yMODULE; } + "medium" { FL; return ygenSTRENGTH; } "module" { FL; return yMODULE; } "nand" { FL; return yNAND; } "negedge" { FL; return yNEGEDGE; } @@ -322,12 +330,15 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "pmos" { FL; return yPMOS; } "posedge" { FL; return yPOSEDGE; } "primitive" { FL; return yPRIMITIVE; } + "pull0" { FL; return ygenSTRENGTH; } + "pull1" { FL; return ygenSTRENGTH; } "pulldown" { FL; return yPULLDOWN; } "pullup" { FL; return yPULLUP; } "rcmos" { FL; return yRCMOS; } "real" { FL; return yREAL; } "realtime" { FL; return yREALTIME; } "reg" { FL; return yREG; } + "release" { FL; return yRELEASE; } "repeat" { FL; return yREPEAT; } "rnmos" { FL; return yRNMOS; } "rpmos" { FL; return yRPMOS; } @@ -335,8 +346,11 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "rtranif0" { FL; return yRTRANIF0; } "rtranif1" { FL; return yRTRANIF1; } "scalared" { FL; return ySCALARED; } + "small" { FL; return ygenSTRENGTH; } "specify" { FL; return ySPECIFY; } "specparam" { FL; return ySPECPARAM; } + "strong0" { FL; return ygenSTRENGTH; } + "strong1" { FL; return ygenSTRENGTH; } "supply0" { FL; return ySUPPLY0; } "supply1" { FL; return ySUPPLY1; } "table" { yy_push_state(TABLE); FL; return yTABLE; } @@ -348,9 +362,17 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "tri" { FL; return yTRI; } "tri0" { FL; return yTRI0; } "tri1" { FL; return yTRI1; } + "triand" { FL; return yTRIAND; } + "trior" { FL; return yTRIOR; } + "trireg" { FL; return yTRIREG; } "vectored" { FL; return yVECTORED; } + "wait" { FL; return yWAIT; } + "wand" { FL; return yWAND; } + "weak0" { FL; return ygenSTRENGTH; } + "weak1" { FL; return ygenSTRENGTH; } "while" { FL; return yWHILE; } "wire" { FL; return yWIRE; } + "wor" { FL; return yWOR; } "xnor" { FL; return yXNOR; } "xor" { FL; return yXOR; } /* Special errors */ @@ -366,29 +388,6 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "$writeb" { FL; RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $write with %%b format instead: %s",yytext); } "$writeh" { FL; RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $write with %%x format instead: %s",yytext); } "$writeo" { FL; RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $write with %%o format instead: %s",yytext); } - /* Generic unsupported warnings */ - "event" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } - "force" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } - "fork" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } - "highz0" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } - "highz1" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } - "join" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } - "large" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } - "medium" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } - "pull0" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } - "pull1" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } - "release" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } - "small" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } - "strong0" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } - "strong1" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } - "triand" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } - "trior" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } - "trireg" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } - "wait" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } - "wand" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } - "weak0" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } - "weak1" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } - "wor" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } } /* Verilog 2001 */ @@ -453,6 +452,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "$warning" { FL; return yD_WARNING; } /* SV2005 Keywords */ "$unit" { FL; return yD_UNIT; } /* Yes, a keyword, not task */ + "alias" { FL; return yALIAS; } "always_comb" { FL; return yALWAYS_COMB; } "always_ff" { FL; return yALWAYS_FF; } "always_latch" { FL; return yALWAYS_LATCH; } @@ -487,6 +487,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "logic" { FL; return yLOGIC; } "longint" { FL; return yLONGINT; } "modport" { FL; return yMODPORT; } + "null" { FL; return yNULL; } "package" { FL; return yPACKAGE; } "packed" { FL; return yPACKED; } "priority" { FL; return yPRIORITY; } @@ -495,6 +496,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "pure" { FL; return yPURE; } "rand" { FL; return yRAND; } "randc" { FL; return yRANDC; } + "randcase" { FL; return yRANDCASE; } "ref" { FL; return yREF; } "restrict" { FL; return yRESTRICT; } "return" { FL; return yRETURN; } @@ -514,7 +516,6 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /* Generic unsupported warnings */ /* Note assert_strobe was in SystemVerilog 3.1, but removed for SystemVerilog 2005 */ "$root" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } - "alias" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "before" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "bins" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "binsof" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } @@ -538,9 +539,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "local" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "matches" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "new" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } - "null" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "protected" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } - "randcase" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "randomize" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "randsequence" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "sequence" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } @@ -1056,7 +1055,8 @@ void V3ParseImp::lexToken() { //yylval // Set by yylexReadTok() } // If a paren, read another - if (token == yCONST__LEX + if (token == '(' + || token == yCONST__LEX || token == yGLOBAL__LEX // Never put yID_* here; below symbol table resolution would break ) { @@ -1067,8 +1067,13 @@ void V3ParseImp::lexToken() { m_aheadVal = yylval; m_aheadVal.token = nexttok; yylval = curValue; - // Now potentially munge the current token - if (token == yCONST__LEX) { + // Now potentially munge the current token + if (token == '(' && (nexttok == ygenSTRENGTH + || nexttok == ySUPPLY0 + || nexttok == ySUPPLY1)) { + token = yP_PAR__STRENGTH; + } + else if (token == yCONST__LEX) { if (nexttok == yREF) token = yCONST__REF; else token = yCONST__ETC; } diff --git a/src/verilog.y b/src/verilog.y index ada6ede06..f9843b8c1 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -35,7 +35,8 @@ // Pick up new lexer #define yylex PARSEP->lexToBison -#define GATEUNSUP(fl,tok) { if (!v3Global.opt.bboxUnsup()) { (fl)->v3error("Unsupported: Verilog 1995 gate primitive: "<<(tok)); } } +#define BBUNSUP(fl,msg) { if (!v3Global.opt.bboxUnsup()) { (fl)->v3error(msg); } } +#define GATEUNSUP(fl,tok) { BBUNSUP((fl), "Unsupported: Verilog 1995 gate primitive: "<<(tok)); } extern void yyerror(const char* errmsg); extern void yyerrorf(const char* format, ...); @@ -242,6 +243,8 @@ class AstSenTree; %token yaTIMINGSPEC "TIMING SPEC ELEMENT" +%token ygenSTRENGTH "STRENGTH keyword (strong1/etc)" + %token yaTABLELINE "TABLE LINE" %token yaSCHDR "`systemc_header BLOCK" @@ -299,9 +302,10 @@ class AstSenTree; // for example yP_ for punctuation based operators. // Double underscores "yX__Y" means token X followed by Y, // and "yX__ETC" means X folled by everything but Y(s). +%token yALIAS "alias" %token yALWAYS "always" -%token yALWAYS_FF "always_ff" %token yALWAYS_COMB "always_comb" +%token yALWAYS_FF "always_ff" %token yALWAYS_LATCH "always_latch" %token yAND "and" %token yASSERT "assert" @@ -321,10 +325,10 @@ class AstSenTree; %token yCASEZ "casez" %token yCHANDLE "chandle" %token yCLOCKING "clocking" +%token yCMOS "cmos" %token yCONST__ETC "const" %token yCONST__LEX "const-in-lex" %token yCONST__REF "const-then-ref" -%token yCMOS "cmos" %token yCONTEXT "context" %token yCONTINUE "continue" %token yCOVER "cover" @@ -350,12 +354,15 @@ class AstSenTree; %token yENDTABLE "endtable" %token yENDTASK "endtask" %token yENUM "enum" +%token yEVENT "event" %token yEXPORT "export" %token yEXTERN "extern" %token yFINAL "final" %token yFOR "for" +%token yFORCE "force" %token yFOREACH "foreach" %token yFOREVER "forever" +%token yFORK "fork" %token yFORKJOIN "forkjoin" %token yFUNCTION "function" %token yGENERATE "generate" @@ -372,6 +379,7 @@ class AstSenTree; %token yINT "int" %token yINTEGER "integer" %token yINTERFACE "interface" +%token yJOIN "join" %token yLOCALPARAM "localparam" %token yLOGIC "logic" %token yLONGINT "longint" @@ -384,6 +392,7 @@ class AstSenTree; %token yNOT "not" %token yNOTIF0 "notif0" %token yNOTIF1 "notif1" +%token yNULL "null" %token yOR "or" %token yOUTPUT "output" %token yPACKAGE "package" @@ -400,11 +409,13 @@ class AstSenTree; %token yPURE "pure" %token yRAND "rand" %token yRANDC "randc" +%token yRANDCASE "randcase" %token yRCMOS "rcmos" %token yREAL "real" %token yREALTIME "realtime" %token yREF "ref" %token yREG "reg" +%token yRELEASE "release" %token yREPEAT "repeat" %token yRESTRICT "restrict" %token yRETURN "return" @@ -435,6 +446,9 @@ class AstSenTree; %token yTRI "tri" %token yTRI0 "tri0" %token yTRI1 "tri1" +%token yTRIAND "triand" +%token yTRIOR "trior" +%token yTRIREG "trireg" %token yTRUE "true" %token yTYPE "type" %token yTYPEDEF "typedef" @@ -445,8 +459,11 @@ class AstSenTree; %token yVAR "var" %token yVECTORED "vectored" %token yVOID "void" +%token yWAIT "wait" +%token yWAND "wand" %token yWHILE "while" %token yWIRE "wire" +%token yWOR "wor" %token yWREAL "wreal" %token yXNOR "xnor" %token yXOR "xor" @@ -568,6 +585,8 @@ class AstSenTree; %token yP_SSRIGHT ">>>" %token yP_POW "**" +%token yP_PAR__STRENGTH "(-for-strength" + %token yP_PLUSCOLON "+:" %token yP_MINUSCOLON "-:" %token yP_MINUSGT "->" @@ -609,6 +628,9 @@ class AstSenTree; // '( is not a operator, as "' (" is legal //******************** +// These prevent other conflicts +%left yP_ANDANDAND + // PSL op precedence %right yP_MINUSGT yP_LOGIFF %right yP_ORMINUSGT yP_OREQGT @@ -822,7 +844,7 @@ module_declaration: // ==IEEE: module_declaration GRAMMARP->endLabel($7,$1,$7); } // | yEXTERN modFront parameter_port_listE portsStarE ';' - { $1->v3error("Unsupported: extern module"); } + { BBUNSUP($1, "Unsupported: extern module"); } ; modFront: @@ -913,9 +935,9 @@ port: // ==IEEE: port VARDTYPE(new AstIfaceRefDType($2,"",*$2,*$4)); $$->addNextNull(VARDONEP($$,$6,$7)); } | portDirNetE yINTERFACE portSig rangeListE sigAttrListE - { $2->v3error("Unsupported: virtual or generic interfaces"); $$=NULL; } + { $$ = NULL; BBUNSUP($2, "Unsupported: virtual or generic interfaces"); } | portDirNetE yINTERFACE '.' idAny/*modport*/ portSig rangeListE sigAttrListE - { $2->v3error("Unsupported: virtual or generic interfaces"); $$=NULL; } + { $$ = NULL; BBUNSUP($2, "Unsupported: virtual or generic interfaces"); } // // // IEEE: ansi_port_declaration, with [port_direction] removed // // IEEE: [ net_port_header | interface_port_header ] port_identifier { unpacked_dimension } [ '=' constant_expression ] @@ -1007,7 +1029,7 @@ interface_declaration: // IEEE: interface_declaration + interface_nonansi_heade if ($5) $1->addStmtp($5); SYMP->popScope($1); } | yEXTERN intFront parameter_port_listE portsStarE ';' - { $1->v3error("Unsupported: extern interface"); } + { BBUNSUP($1, "Unsupported: extern interface"); } ; intFront: @@ -1034,8 +1056,10 @@ interface_item: // IEEE: interface_item + non_port_interface_item // // IEEE: generate_region | interface_generate_region { $$ = $1; } | interface_or_generate_item { $$ = $1; } - //UNSUP program_declaration { $$ = $1; } - //UNSUP interface_declaration { $$ = $1; } + | program_declaration { $$ = NULL; v3error("Unsupported: program decls within interface decls"); } + // // IEEE 1800-2017: modport_item + // // See instead old 2012 position in interface_or_generate_item + | interface_declaration { $$ = NULL; v3error("Unsupported: interface decls within interface decls"); } | timeunits_declaration { $$ = $1; } // // See note in interface_or_generate item | module_common_item { $$ = $1; } @@ -1090,7 +1114,7 @@ program_declaration: // IEEE: program_declaration + program_nonansi_header + pr SYMP->popScope($1); GRAMMARP->endLabel($7,$1,$7); } | yEXTERN pgmFront parameter_port_listE portsStarE ';' - { $1->v3error("Unsupported: extern program"); + { BBUNSUP($1, "Unsupported: extern program"); SYMP->popScope($2); } ; @@ -1135,9 +1159,9 @@ program_generate_item: // ==IEEE: program_generate_item ; extern_tf_declaration: // ==IEEE: extern_tf_declaration - yEXTERN task_prototype ';' { $1->v3error("Unsupported: extern task"); $$ = NULL; } - | yEXTERN function_prototype ';' { $1->v3error("Unsupported: extern function"); $$ = NULL; } - | yEXTERN yFORKJOIN task_prototype ';' { $1->v3error("Unsupported: extern forkjoin"); $$ = NULL; } + yEXTERN task_prototype ';' { $$ = NULL; BBUNSUP($1, "Unsupported: extern task"); } + | yEXTERN function_prototype ';' { $$ = NULL; BBUNSUP($1, "Unsupported: extern function"); } + | yEXTERN yFORKJOIN task_prototype ';' { $$ = NULL; BBUNSUP($1, "Unsupported: extern forkjoin"); } ; modport_declaration: // ==IEEE: modport_declaration @@ -1167,14 +1191,14 @@ modportPortsDecl: // // IEEE: modport_simple_ports_declaration port_direction modportSimplePort { $$ = new AstModportVarRef($1,*$2,GRAMMARP->m_varIO); } // // IEEE: modport_clocking_declaration - | yCLOCKING idAny/*clocking_identifier*/ { $1->v3error("Unsupported: Modport clocking"); } + | yCLOCKING idAny/*clocking_identifier*/ { $$ = NULL; BBUNSUP($1, "Unsupported: Modport clocking"); } // // IEEE: yIMPORT modport_tf_port // // IEEE: yEXPORT modport_tf_port // // modport_tf_port expanded here | yIMPORT id/*tf_identifier*/ { $$ = new AstModportFTaskRef($1,*$2,false); } | yEXPORT id/*tf_identifier*/ { $$ = new AstModportFTaskRef($1,*$2,true); } - | yIMPORT method_prototype { $1->v3error("Unsupported: Modport import with prototype"); } - | yEXPORT method_prototype { $1->v3error("Unsupported: Modport export with prototype"); } + | yIMPORT method_prototype { $$ = NULL; BBUNSUP($1, "Unsupported: Modport import with prototype"); } + | yEXPORT method_prototype { $$ = NULL; BBUNSUP($1, "Unsupported: Modport export with prototype"); } // Continuations of above after a comma. // // IEEE: modport_simple_ports_declaration | modportSimplePort { $$ = new AstModportVarRef($1,*$1,GRAMMARP->m_varIO); } @@ -1263,7 +1287,7 @@ net_declRESET: net_scalaredE: /* empty */ { } - //UNSUP: ySCALARED/yVECTORED ignored + // //UNSUP: ySCALARED/yVECTORED ignored | ySCALARED { } | yVECTORED { } ; @@ -1284,12 +1308,12 @@ net_type: // ==IEEE: net_type | yTRI { VARDECL(TRIWIRE); } | yTRI0 { VARDECL(TRI0); } | yTRI1 { VARDECL(TRI1); } - //UNSUP yTRIAND { VARDECL(TRIAND); } - //UNSUP yTRIOR { VARDECL(TRIOR); } - //UNSUP yTRIREG { VARDECL(TRIREG); } - //UNSUP yWAND { VARDECL(WAND); } + | yTRIAND { VARDECL(WIRE); BBUNSUP($1, "Unsupported: triand"); } + | yTRIOR { VARDECL(WIRE); BBUNSUP($1, "Unsupported: trior"); } + | yTRIREG { VARDECL(WIRE); BBUNSUP($1, "Unsupported: trireg"); } + | yWAND { VARDECL(WIRE); BBUNSUP($1, "Unsupported: wand"); } | yWIRE { VARDECL(WIRE); } - //UNSUP yWOR { VARDECL(WOR); } + | yWOR { VARDECL(WIRE); BBUNSUP($1, "Unsupported: wor"); } // // VAMS - somewhat hackish | yWREAL { VARDECL(WREAL); } ; @@ -1373,7 +1397,7 @@ integer_vector_type: // ==IEEE: integer_atom_type non_integer_type: // ==IEEE: non_integer_type yREAL { $$ = new AstBasicDType($1,AstBasicDTypeKwd::DOUBLE); } | yREALTIME { $$ = new AstBasicDType($1,AstBasicDTypeKwd::DOUBLE); } - | ySHORTREAL { $1->v3error("Unsupported: shortreal (use real instead)"); + | ySHORTREAL { BBUNSUP($1, "Unsupported: shortreal (use real instead)"); $$ = new AstBasicDType($1,AstBasicDTypeKwd::DOUBLE); } ; @@ -1441,7 +1465,7 @@ data_typeNoRef: // ==IEEE: data_type, excluding class_type etc referenc SYMP,VFlagChildDType(),$1); } | ySTRING { $$ = new AstBasicDType($1,AstBasicDTypeKwd::STRING); } | yCHANDLE { $$ = new AstBasicDType($1,AstBasicDTypeKwd::CHANDLE); } - //UNSUP yEVENT { UNSUP } + | yEVENT { $$ = new AstBasicDType($1,AstBasicDTypeKwd::BIT); BBUNSUP($1, "Unsupported: event data types"); } //UNSUP yVIRTUAL__INTERFACE yINTERFACE id/*interface*/ { UNSUP } //UNSUP yVIRTUAL__anyID id/*interface*/ { UNSUP } //UNSUP type_reference { UNSUP } @@ -1742,9 +1766,9 @@ non_port_module_item: // ==IEEE: non_port_module_item | module_or_generate_item { $$ = $1; } | specify_block { $$ = $1; } | specparam_declaration { $$ = $1; } - //UNSUP program_declaration { $$ = $1; } - //UNSUP module_declaration { $$ = $1; } - //UNSUP interface_declaration { $$ = $1; } + | program_declaration { $$ = NULL; v3error("Unsupported: program decls within module decls"); } + | module_declaration { $$ = NULL; v3error("Unsupported: module decls within module decls"); } + | interface_declaration { $$ = NULL; v3error("Unsupported: interface decls within module decls"); } | timeunits_declaration { $$ = $1; } // // Verilator specific | yaSCHDR { $$ = new AstScHdr($1,*$1); } @@ -1779,7 +1803,7 @@ module_common_item: // ==IEEE: module_common_item | bind_directive { $$ = $1; } | continuous_assign { $$ = $1; } // // IEEE: net_alias - //UNSUP yALIAS variable_lvalue aliasEqList ';' { UNSUP } + | yALIAS variable_lvalue aliasEqList ';' { $$ = NULL; BBUNSUP($1, "Unsupported: alias statements"); } | initial_construct { $$ = $1; } | final_construct { $$ = $1; } // // IEEE: always_construct @@ -1812,14 +1836,20 @@ module_or_generate_item_declaration: // ==IEEE: module_or_generate_item_d package_or_generate_item_declaration { $$ = $1; } | genvar_declaration { $$ = $1; } | clocking_declaration { $$ = $1; } - //UNSUP yDEFAULT yCLOCKING idAny/*new-clocking_identifier*/ ';' { $$ = $1; } + | yDEFAULT yCLOCKING idAny/*new-clocking_identifier*/ ';' { $$ = NULL; BBUNSUP($1, "Unsupported: default clocking identifier"); } + ; + +aliasEqList: // IEEE: part of net_alias + '=' variable_lvalue { } + | aliasEqList '=' variable_lvalue { } ; bind_directive: // ==IEEE: bind_directive + bind_target_scope // // ';' - Note IEEE grammar is wrong, includes extra ';' - it's already in module_instantiation // // We merged the rules - id may be a bind_target_instance or module_identifier or interface_identifier yBIND bind_target_instance bind_instantiation { $$ = new AstBind($1,*$2,$3); } - | yBIND bind_target_instance ':' bind_target_instance_list bind_instantiation { $$=NULL; $1->v3error("Unsupported: Bind with instance list"); } + | yBIND bind_target_instance ':' bind_target_instance_list bind_instantiation { + $$=NULL; BBUNSUP($1, "Unsupported: Bind with instance list"); } ; bind_target_instance_list: // ==IEEE: bind_target_instance_list @@ -2077,7 +2107,7 @@ packed_dimensionList: // IEEE: { packed_dimension } packed_dimension: // ==IEEE: packed_dimension anyrange { $$ = $1; } - | '[' ']' { $1->v3error("Unsupported: [] dimensions"); $$ = NULL; } + | '[' ']' { $$ = NULL; $1->v3error("Unsupported: [] dimensions"); } ; //************************************************ @@ -2306,11 +2336,23 @@ seq_block: // ==IEEE: seq_block | seq_blockFront /**/ yEND endLabelE { $$=$1; SYMP->popScope($1); GRAMMARP->endLabel($3,$1,$3); } ; -seq_blockFront: // IEEE: part of par_block +par_block: // ==IEEE: par_block + par_blockFront blockDeclStmtList yJOIN endLabelE { $$=$1; $1->addStmtsp($2); SYMP->popScope($1); GRAMMARP->endLabel($4,$1,$4); } + | par_blockFront /**/ yJOIN endLabelE { $$=$1; SYMP->popScope($1); GRAMMARP->endLabel($3,$1,$3); } + ; + +seq_blockFront: // IEEE: part of seq_block yBEGIN { $$ = new AstBegin($1,"",NULL); SYMP->pushNew($$); } | yBEGIN ':' idAny/*new-block_identifier*/ { $$ = new AstBegin($1,*$3,NULL); SYMP->pushNew($$); } ; +par_blockFront: // IEEE: part of par_block + yFORK { $$ = new AstBegin($1, "", NULL); SYMP->pushNew($$); + BBUNSUP($1, "Unsupported: fork statements"); } + | yFORK ':' idAny/*new-block_identifier*/ { $$ = new AstBegin($1,*$3,NULL); SYMP->pushNew($$); + BBUNSUP($1, "Unsupported: fork statements"); } + ; + blockDeclStmtList: // IEEE: { block_item_declaration } { statement or null } // // The spec seems to suggest a empty declaration isn't ok, but most simulators take it block_item_declarationList { $$ = $1; } @@ -2360,10 +2402,9 @@ statement_item: // IEEE: statement_item // // IEEE: procedural_continuous_assignment | yASSIGN idClassSel '=' delayE expr ';' { $$ = new AstAssign($1,$2,$5); } //UNSUP: delay_or_event_controlE above - | yDEASSIGN variable_lvalue ';' { if (!v3Global.opt.bboxUnsup()) $1->v3error("Unsupported: Verilog 1995 deassign"); $$ = NULL; } - - //UNSUP yFORCE expr '=' expr ';' { UNSUP } - //UNSUP yRELEASE variable_lvalue ';' { UNSUP } + | yDEASSIGN variable_lvalue ';' { $$ = NULL; BBUNSUP($1, "Unsupported: Verilog 1995 deassign"); } + | yFORCE expr '=' expr ';' { $$ = NULL; BBUNSUP($1, "Unsupported: Verilog 1995 force"); } + | yRELEASE variable_lvalue ';' { $$ = NULL; BBUNSUP($1, "Unsupported: Verilog 1995 release"); } // // // IEEE: case_statement | unique_priorityE caseStart caseAttrE case_itemListE yENDCASE { $$ = $2; if ($4) $2->addItemsp($4); @@ -2428,7 +2469,7 @@ statement_item: // IEEE: statement_item // // // IEEE: disable_statement | yDISABLE idAny/*hierarchical_identifier-task_or_block*/ ';' { $$ = new AstDisable($1,*$2); } - //UNSUP yDISABLE yFORK ';' { UNSUP } + | yDISABLE yFORK ';' { $$ = NULL; BBUNSUP($1, "Unsupported: disable fork statements"); } // // IEEE: event_trigger //UNSUP yP_MINUSGT hierarchical_identifier/*event*/ ';' { UNSUP } //UNSUP yP_MINUSGTGT delay_or_event_controlE hierarchical_identifier/*event*/ ';' { UNSUP } @@ -2452,7 +2493,7 @@ statement_item: // IEEE: statement_item | yBREAK ';' { $$ = new AstBreak($1); } | yCONTINUE ';' { $$ = new AstContinue($1); } // - //UNSUP par_block { $$ = $1; } + | par_block { $$ = $1; } // // IEEE: procedural_timing_control_statement + procedural_timing_control | delay_control stmtBlock { $$ = $2; $1->v3warn(STMTDLY,"Unsupported: Ignoring delay on this delayed statement."); } //UNSUP event_control stmtBlock { UNSUP } @@ -2461,8 +2502,8 @@ statement_item: // IEEE: statement_item | seq_block { $$ = $1; } // // // IEEE: wait_statement - //UNSUP yWAIT '(' expr ')' stmtBlock { UNSUP } - //UNSUP yWAIT yFORK ';' { UNSUP } + | yWAIT '(' expr ')' stmtBlock { $$ = NULL; BBUNSUP($1, "Unsupported: wait statements"); } + | yWAIT yFORK ';' { $$ = NULL; BBUNSUP($1, "Unsupported: wait fork statements"); } //UNSUP yWAIT_ORDER '(' hierarchical_identifierList ')' action_block { UNSUP } // // // IEEE: procedural_assertion_statement @@ -2478,7 +2519,7 @@ statement_item: // IEEE: statement_item //UNSUP randsequence_statement { $$ = $1; } // // // IEEE: randcase_statement - //UNSUP yRANDCASE case_itemList yENDCASE { UNSUP } + | yRANDCASE case_itemList yENDCASE { $$ = NULL; BBUNSUP($1, "Unsupported: SystemVerilog 2005 randcase statements"); } // //UNSUP expect_property_statement { $$ = $1; } // @@ -2596,11 +2637,11 @@ caseCondList: // IEEE: part of case_item ; patternNoExpr: // IEEE: pattern **Excluding Expr* - '.' id/*variable*/ { $1->v3error("Unsupported: '{} tagged patterns"); $$=NULL; } - | yP_DOTSTAR { $1->v3error("Unsupported: '{} tagged patterns"); $$=NULL; } + '.' id/*variable*/ { $$ = NULL; $1->v3error("Unsupported: '{} tagged patterns"); } + | yP_DOTSTAR { $$ = NULL; $1->v3error("Unsupported: '{} tagged patterns"); } // // IEEE: "expr" excluded; expand in callers // // "yTAGGED id [expr]" Already part of expr - //UNSUP yTAGGED id/*member_identifier*/ patternNoExpr { $1->v3error("Unsupported: '{} tagged patterns"); $$=NULL; } + //UNSUP yTAGGED id/*member_identifier*/ patternNoExpr { $$ = NULL; $1->v3error("Unsupported: '{} tagged patterns"); } // // "yP_TICKBRA patternList '}'" part of expr under assignment_pattern ; @@ -2622,10 +2663,10 @@ patternMemberList: // IEEE: part of pattern and assignment_pattern patternMemberOne: // IEEE: part of pattern and assignment_pattern patternKey ':' expr { $$ = new AstPatMember($2,$3,$1,NULL); } - | patternKey ':' patternNoExpr { $2->v3error("Unsupported: '{} .* patterns"); $$=NULL; } + | patternKey ':' patternNoExpr { $$ = NULL; $2->v3error("Unsupported: '{} .* patterns"); } // // From assignment_pattern_key | yDEFAULT ':' expr { $$ = new AstPatMember($2,$3,NULL,NULL); $$->isDefault(true); } - | yDEFAULT ':' patternNoExpr { $2->v3error("Unsupported: '{} .* patterns"); $$=NULL; } + | yDEFAULT ':' patternNoExpr { $$ = NULL; $2->v3error("Unsupported: '{} .* patterns"); } ; patternKey: // IEEE: merge structure_pattern_key, array_pattern_key, assignment_pattern_key @@ -2657,7 +2698,7 @@ assignment_pattern: // ==IEEE: assignment_pattern // // also IEEE "''{' array_pattern_key ':' ... | yP_TICKBRA patternMemberList '}' { $$ = new AstPattern($1,$2); } // // IEEE: Not in grammar, but in VMM - | yP_TICKBRA '}' { $1->v3error("Unsupported: Empty '{}"); $$=NULL; } + | yP_TICKBRA '}' { $$ = NULL; $1->v3error("Unsupported: Empty '{}"); } ; // "datatype id = x {, id = x }" | "yaId = x {, id=x}" is legal @@ -2755,7 +2796,7 @@ system_t_call: // IEEE: system_tf_call (as task) | yD_SYSTEM '(' expr ')' { $$ = new AstSystemT($1,$3); } // | yD_FCLOSE '(' idClassSel ')' { $$ = new AstFClose($1, $3); } - | yD_FFLUSH parenE { $1->v3error("Unsupported: $fflush of all handles does not map to C++."); } + | yD_FFLUSH parenE { $$ = NULL; BBUNSUP($1, "Unsupported: $fflush of all handles does not map to C++."); } | yD_FFLUSH '(' expr ')' { $$ = new AstFFlush($1, $3); } | yD_FINISH parenE { $$ = new AstFinish($1); } | yD_FINISH '(' expr ')' { $$ = new AstFinish($1); DEL($3); } @@ -2856,7 +2897,7 @@ system_f_call_or_t: // IEEE: part of system_tf_call (can be task or func) | yD_PAST '(' expr ',' expr ',' expr ')' { $1->v3error("Unsupported: $past expr2 and clock arguments"); $$ = $3; } | yD_PAST '(' expr ',' expr ',' expr ',' expr')' { $1->v3error("Unsupported: $past expr2 and clock arguments"); $$ = $3; } | yD_POW '(' expr ',' expr ')' { $$ = new AstPowD($1,$3,$5); } - | yD_RANDOM '(' expr ')' { $1->v3error("Unsupported: Seeding $random doesn't map to C++, use $c(\"srand\")"); $$ = NULL; } + | yD_RANDOM '(' expr ')' { $$ = NULL; $1->v3error("Unsupported: Seeding $random doesn't map to C++, use $c(\"srand\")"); } | yD_RANDOM parenE { $$ = new AstRand($1); } | yD_REALTIME parenE { $$ = new AstTimeD($1); } | yD_REALTOBITS '(' expr ')' { $$ = new AstRealToBits($1,$3); } @@ -3218,7 +3259,8 @@ expr: // IEEE: part of expression/constant_expression/primary // // IEEE: "... hierarchical_identifier select" see below // // // IEEE: empty_queue (IEEE 1800-2017 empty_unpacked_array_concatenation) - //UNSUP '{' '}' + | '{' '}' { $$ = new AstConst($1, AstConst::LogicFalse()); + $1->v3error("Unsupported: empty queues (\"{ }\")"); } // // // IEEE: concatenation/constant_concatenation // // Part of exprOkLvalue below @@ -3237,7 +3279,7 @@ expr: // IEEE: part of expression/constant_expression/primary // // // IEEE: '(' mintypmax_expression ')' | ~noPar__IGNORE~'(' expr ')' { $$ = $2; } - //UNSUP ~noPar__IGNORE~'(' expr ':' expr ':' expr ')' { $$ = $4; } + | ~noPar__IGNORE~'(' expr ':' expr ':' expr ')' { $$ = $2; BBUNSUP($1, "Unsupported: min typ max expressions"); } // // PSL rule | '_' '(' expr ')' { $$ = $3; } // Arbitrary Verilog inside PSL // @@ -3257,8 +3299,10 @@ expr: // IEEE: part of expression/constant_expression/primary // // IEEE: sequence_method_call // // Indistinguishable from function_subroutine_call:method_call // - //UNSUP '$' { UNSUP } - //UNSUP yNULL { UNSUP } + | '$' { $$ = new AstConst($1, AstConst::LogicFalse()); + $1->v3error("Unsupported: $ expression"); } + | yNULL { $$ = new AstConst($1, AstConst::LogicFalse()); + $1->v3error("Unsupported: null expression"); } // // IEEE: yTHIS // // See exprScope // @@ -3271,7 +3315,8 @@ expr: // IEEE: part of expression/constant_expression/primary // // // IEEE: cond_predicate - here to avoid reduce problems // // Note expr includes cond_pattern - //UNSUP ~l~expr yP_ANDANDAND ~r~expr { UNSUP } + | ~l~expr yP_ANDANDAND ~r~expr { $$ = new AstConst($2, AstConst::LogicFalse()); + $2->v3error("Unsupported: &&& expression"); } // // // IEEE: cond_pattern - here to avoid reduce problems // // "expr yMATCHES pattern" @@ -3630,9 +3675,21 @@ gatePinExpr: expr { $$ = GRAMMARP ->createGatePin($1); } ; +// This list is also hardcoded in VParseLex.l +strength: // IEEE: strength0+strength1 - plus HIGHZ/SMALL/MEDIUM/LARGE + ygenSTRENGTH { BBUNSUP($1, "Unsupported: Verilog 1995 strength specifiers"); } + | ySUPPLY0 { BBUNSUP($1, "Unsupported: Verilog 1995 strength specifiers"); } + | ySUPPLY1 { BBUNSUP($1, "Unsupported: Verilog 1995 strength specifiers"); } + ; + strengthSpecE: // IEEE: drive_strength + pullup_strength + pulldown_strength + charge_strength - plus empty /* empty */ { } - //UNSUP strengthSpec { } + | strengthSpec { } + ; + +strengthSpec: // IEEE: drive_strength + pullup_strength + pulldown_strength + charge_strength - plus empty + yP_PAR__STRENGTH strength ')' { } + | yP_PAR__STRENGTH strength ',' strength ')' { } ; //************************************************ @@ -3826,7 +3883,7 @@ procedural_assertion_statement: // ==IEEE: procedural_assertion_statement | immediate_assertion_statement { $$ = $1; } // // IEEE: checker_instantiation // // Unlike modules, checkers are the only "id id (...)" form in statements. - //UNSUP checker_instantiation { } + //UNSUP checker_instantiation { $$ = $1; } ; immediate_assertion_statement: // ==IEEE: immediate_assertion_statement @@ -3844,7 +3901,7 @@ simple_immediate_assertion_statement: // ==IEEE: simple_immediate_asserti | yASSUME '(' expr ')' yELSE stmtBlock { $$ = new AstVAssert($1,$3,NULL,$6); } | yASSUME '(' expr ')' stmtBlock yELSE stmtBlock { $$ = new AstVAssert($1,$3,$5,$7); } // // IEEE: simple_immediate_cover_statement - | yCOVER '(' expr ')' stmt { $1->v3error("Unsupported: immediate cover"); $$=NULL; } + | yCOVER '(' expr ')' stmt { $$ = NULL; BBUNSUP($1, "Unsupported: immediate cover"); } ; final_zero: // IEEE: part of deferred_immediate_assertion_statement @@ -3864,7 +3921,7 @@ deferred_immediate_assertion_statement: // ==IEEE: deferred_immediate_ass | yASSUME final_zero '(' expr ')' yELSE stmtBlock { $$ = new AstVAssert($1,$4,NULL,$7); } | yASSUME final_zero '(' expr ')' stmtBlock yELSE stmtBlock { $$ = new AstVAssert($1,$4,$6,$8); } // // IEEE: deferred_immediate_cover_statement - | yCOVER final_zero '(' expr ')' stmt { $1->v3error("Unsupported: immediate cover"); $$=NULL; } + | yCOVER final_zero '(' expr ')' stmt { $$ = NULL; BBUNSUP($1, "Unsupported: immediate cover"); } ; concurrent_assertion_item: // IEEE: concurrent_assertion_item