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Merge branch 'master' of ssh://git-verilator-wsnyder/git/verilator
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commit
8ff2bf51c5
7
Changes
7
Changes
@ -4,7 +4,12 @@ The contributors that suggested a given feature are shown in []. [by ...]
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indicates the contributor was also the author of the fix; Thanks!
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* Verilator 3.825***
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* Verilator 3.831****
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**** Suppress VARHIDDEN on dpi import arguments. [Ruben Diez]
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* Verilator 3.830 2011/11/27
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** With "--language VAMS" support a touch of Verilog AMS. [Holger Waechtler]
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@ -4,7 +4,7 @@
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# redistribute it and/or modify it under the terms of either the GNU Lesser
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# General Public License Version 3 or the Perl Artistic License Version 2.0.
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AC_INIT([Verilator],[3.825 devel])
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AC_INIT([Verilator],[3.831 devel])
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AC_CONFIG_HEADER(src/config_build.h)
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AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk)
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@ -319,7 +319,8 @@ private:
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}
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} else {
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// User can disable the message at either point
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if (!nodep->fileline()->warnIsOff(V3ErrorCode::VARHIDDEN)
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if (!(m_ftaskp && m_ftaskp->dpiImport())
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&& !nodep->fileline()->warnIsOff(V3ErrorCode::VARHIDDEN)
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&& !foundp->fileline()->warnIsOff(V3ErrorCode::VARHIDDEN)) {
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nodep->v3warn(VARHIDDEN,"Declaration of signal hides declaration in upper scope: "<<nodep->name());
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foundp->v3warn(VARHIDDEN,"... Location of original declaration");
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@ -1375,6 +1375,7 @@ non_port_module_item<nodep>: // ==IEEE: non_port_module_item
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generate_region<nodep>: // ==IEEE: generate_region
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yGENERATE genTopBlock yENDGENERATE { $$ = new AstGenerate($1, $2); }
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| yGENERATE yENDGENERATE { $$ = NULL; }
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;
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module_or_generate_item<nodep>: // ==IEEE: module_or_generate_item
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@ -93,6 +93,9 @@ module paramed (/*AUTOARG*/
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for (i=0; i<3; i=i+1) begin end
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endgenerate
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generate
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endgenerate
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generate
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if (MODE==0) begin
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// Flip bitorder, direct assign method
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@ -5,6 +5,11 @@
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module t;
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// Arguable, but we won't throw a hidden warning on tcp_port
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parameter tcp_port = 5678;
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import "DPI-C" function int dpii_func ( input integer tcp_port,
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output longint obj );
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// 't' is hidden:
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integer t;
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endmodule
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