From 8f1798cc6f0fc69ac353aa724be00024c5ec4a9f Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 28 Nov 2017 19:11:41 -0500
Subject: [PATCH] Fix modport outputs being treated as inputs, bug1246.

---
 Changes                                   |  2 ++
 src/verilog.y                             |  5 +++--
 test_regress/t/t_interface_modportlist.pl | 18 ++++++++++++++++++
 test_regress/t/t_interface_modportlist.v  | 23 +++++++++++++++++++++++
 4 files changed, 46 insertions(+), 2 deletions(-)
 create mode 100755 test_regress/t/t_interface_modportlist.pl
 create mode 100644 test_regress/t/t_interface_modportlist.v

diff --git a/Changes b/Changes
index 1ec8448e0..978fc22a4 100644
--- a/Changes
+++ b/Changes
@@ -4,6 +4,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 * Verilator 3.917 devel
 
+****   Fix modport outputs being treated as inputs, bug1246. [Jeff Bush]
+
 
 * Verilator 3.916 2017-11-25
 
diff --git a/src/verilog.y b/src/verilog.y
index 6155e4090..addc8626e 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1087,7 +1087,8 @@ modport_itemList<nodep>:		// IEEE: part of modport_declaration
 	;
 
 modport_item<nodep>:			// ==IEEE: modport_item
-		id/*new-modport*/ '(' modportPortsDeclList ')'		{ $$ = new AstModport($2,*$1,$3); }
+		id/*new-modport*/ '(' { VARRESET_NONLIST(UNKNOWN); VARIO(INOUT); }
+	/*cont*/	modportPortsDeclList ')'	{ $$ = new AstModport($2,*$1,$4); }
 	;
 
 modportPortsDeclList<nodep>:
@@ -1113,7 +1114,7 @@ modportPortsDecl<nodep>:
 	|	yEXPORT method_prototype		{ $1->v3error("Unsupported: Modport export with prototype"); }
 	// Continuations of above after a comma.
 	//			// IEEE: modport_simple_ports_declaration
-	|	modportSimplePort			{ $$ = new AstModportVarRef($<fl>1,*$1,AstVarType::INOUT); }
+	|	modportSimplePort			{ $$ = new AstModportVarRef($<fl>1,*$1,GRAMMARP->m_varIO); }
 	;
 
 modportSimplePort<strp>:	// IEEE: modport_simple_port or modport_tf_port, depending what keyword was earlier
diff --git a/test_regress/t/t_interface_modportlist.pl b/test_regress/t/t_interface_modportlist.pl
new file mode 100755
index 000000000..9245a95fe
--- /dev/null
+++ b/test_regress/t/t_interface_modportlist.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    fails=>0,
+    verilator_make_gcc => 0,
+    make_top_shell => 0,
+    make_main => 0,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_interface_modportlist.v b/test_regress/t/t_interface_modportlist.v
new file mode 100644
index 000000000..20ac0241e
--- /dev/null
+++ b/test_regress/t/t_interface_modportlist.v
@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2016 by Adrian Wise
+
+//bug1246
+
+module t(input clk);
+   my_interface iface();
+   my_module m(.clk(clk), iface);
+endmodule
+
+module my_module(input clk, my_interface.my_port iface);
+   always @(posedge clk) begin
+      iface.b <= iface.a;
+      iface.c <= iface.a;
+   end
+endmodule
+
+interface my_interface;
+   logic a, b, c;
+   modport my_port(input a, output b, c);
+endinterface