github/verilator
1
0
Fork 1
mirror of https://github.com/verilator/verilator.git synced 2025-04-25 10:06:54 +00:00
Code Issues Packages Projects Releases Wiki Activity

Tests: Resolve racing among initial blocks in t_display_signed.v, #2144.

Browse Source
This commit is contained in:
Yutetsu TAKATSUKASA 2020-01-30 07:07:45 +09:00 committed by GitHub
parent d4614c290e
commit 8d8eb1b9f3
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 13 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
test_regress/t/t_display_signed.v
View File

@ -4,14 +4,21 @@
// without warranty, 2003 by Wilson Snyder.
module t;
reg signed [20:0] longp; initial longp = 21'shbbccc;
reg signed [20:0] longn; initial longn = 21'shbbccc; initial longn[20]=1'b1;
reg signed [40:0] quadp; initial quadp = 41'sh1_bbbb_cccc;
reg signed [40:0] quadn; initial quadn = 41'sh1_bbbb_cccc; initial quadn[40]=1'b1;
reg signed [80:0] widep; initial widep = 81'shbc_1234_5678_1234_5678;
reg signed [80:0] widen; initial widen = 81'shbc_1234_5678_1234_5678; initial widen[40]=1'b1;
reg signed [20:0] longp;
reg signed [20:0] longn;
reg signed [40:0] quadp;
reg signed [40:0] quadn;
reg signed [80:0] widep;
reg signed [80:0] widen;
initial begin
longp = 21'shbbccc;
longn = 21'shbbccc; longn[20] = 1'b1;
quadp = 41'sh1_bbbb_cccc;
quadn = 41'sh1_bbbb_cccc; quadn[40] = 1'b1;
widep = 81'shbc_1234_5678_1234_5678;
widen = 81'shbc_1234_5678_1234_5678; widen[40] = 1'b1;
// Display formatting
$display("[%0t] lp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d %%p=%p %%0p=%0p",
$time, longp, longp, longp, longp, longp, longp, longp, longp);