Fix error on UNPACKED in parser. (#1541)

bin/verilator

@@ -4816,7 +4816,10 @@ correctly.
 Warns that unpacked structs and unions are not supported.
 
 Ignoring this warning will make Verilator treat the structure as packed,
-which may make Verilator simulations differ from other simulators.
+which may make Verilator simulations differ from other simulators. This
+downgrading may also result what would normally be a legal unpacked
+struct/array inside an unpacked struct/array becomming an illegal unpacked
+struct/array inside a packed struct/array.
 
 =item UNSIGNED
 

src/verilog.y

@@ -1667,7 +1667,7 @@ list_of_member_decl_assignments<nodep>:	// Derived from IEEE: list_of_variable_d
 member_decl_assignment<memberp>:	// Derived from IEEE: variable_decl_assignment
 	//			// At present we allow only packed structures/unions.  So this is different from variable_decl_assignment
 		id variable_dimensionListE
-			{ if ($2) $2->v3error("Unsupported: Unpacked array in packed struct/union");
+			{ if ($2) $2->v3warn(UNPACKED, "Unsupported: Unpacked array in packed struct/union (struct/union converted to unpacked)");
 			  $$ = new AstMemberDType($<fl>1, *$1, VFlagChildDType(),
 						  AstNodeDType::cloneTreeNull(GRAMMARP->m_memDTypep, true));
                           PARSEP->tagNodep($$);

test_regress/t/t_struct_unpacked2.out

@@ -0,0 +1,8 @@
+%Warning-UNPACKED: t/t_struct_unpacked2.v:10:13: Unsupported: Unpacked array in packed struct/union (struct/union converted to unpacked)
+   10 |       int b [2];
+      |             ^
+                   ... Use "/* verilator lint_off UNPACKED */" and lint_on around source to disable this message.
+%Warning-UNPACKED: t/t_struct_unpacked2.v:9:12: Unsupported: Unpacked struct/union
+    9 |    typedef struct {
+      |            ^~~~~~
+%Error: Exiting due to

test_regress/t/t_struct_unpacked2.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_struct_unpacked2.v

@@ -0,0 +1,21 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2009 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module x;
+
+   typedef struct {
+      int b [2];
+   } notpacked_t;
+
+   notpacked_t n;
+
+   initial begin
+      n.b[0] = 1;
+      if (n.b[0] != 1) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule