From 8ae79066a2f8397cb76e6e9fcdce1da1d1817493 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 15 Mar 2023 21:56:35 -0400
Subject: [PATCH] Fix false ENUMVALUE on expressions and arrays.

---
 Changes                 |  1 +
 src/V3Ast.cpp           |  4 +++-
 test_regress/t/t_0.pl   | 21 +++++++++++++++++++++
 test_regress/t/t_0.v    | 21 +++++++++++++++++++++
 test_regress/t/t_enum.v | 10 ++++++++++
 5 files changed, 56 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_0.pl
 create mode 100644 test_regress/t/t_0.v

diff --git a/Changes b/Changes
index b3da19ca6..a5a130b79 100644
--- a/Changes
+++ b/Changes
@@ -21,6 +21,7 @@ Verilator 5.009 devel
 * Fix UNDRIVEN warning seg fault (#3989). [Felix Neumärker]
 * Fix symbol entries when inheriting classes (#3995) (#3996). [Krzysztof Bieganski, Antmicro Ltd]
 * Fix push to dynamic queue in struct (#4015). [ezchi]
+* Fix false ENUMVALUE on expressions and arrays.
 
 
 Verilator 5.008 2023-03-04
diff --git a/src/V3Ast.cpp b/src/V3Ast.cpp
index db5722c64..8b8fcc7f3 100644
--- a/src/V3Ast.cpp
+++ b/src/V3Ast.cpp
@@ -1342,7 +1342,9 @@ void AstNode::dtypeChgWidthSigned(int width, int widthMin, VSigning numeric) {
         dtypeSetLogicUnsized(width, widthMin, numeric);
     } else {
         if (width == dtypep()->width() && widthMin == dtypep()->widthMin()
-            && numeric == dtypep()->numeric())
+            && numeric == dtypep()->numeric()
+            // Enums need to become direct sizes to avoid later ENUMVALUE errors
+            && !VN_IS(dtypep()->skipRefToEnump(), EnumDType))
             return;  // Correct already
         // FUTURE: We may be pointing at a two state data type, and this may
         // convert it to logic.  Since the AstVar remains correct, we
diff --git a/test_regress/t/t_0.pl b/test_regress/t/t_0.pl
new file mode 100755
index 000000000..b46d46042
--- /dev/null
+++ b/test_regress/t/t_0.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_0.v b/test_regress/t/t_0.v
new file mode 100644
index 000000000..0d26d323e
--- /dev/null
+++ b/test_regress/t/t_0.v
@@ -0,0 +1,21 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2009 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+
+   enum int unsigned {
+      FIVE_INT = 5
+   } FI;
+
+   int array5i[FIVE_INT];
+
+   initial begin
+      if ($size(array5i) != 5) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
diff --git a/test_regress/t/t_enum.v b/test_regress/t/t_enum.v
index 2182ce9de..887866a37 100644
--- a/test_regress/t/t_enum.v
+++ b/test_regress/t/t_enum.v
@@ -31,10 +31,17 @@ module t (/*AUTOARG*/);
          z5 = e5
          } ZN;
 
+   enum int unsigned {
+      FIVE_INT = 5
+   } FI;
+
    typedef enum three_t;  // Forward
    typedef enum [2:0] { ONES=~0 } three_t;
    three_t three = ONES;
 
+   int array5[z5];
+   int array5i[FIVE_INT];
+
    var logic [ONES:0] sized_based_on_enum;
 
    var enum logic [3:0]  { QINVALID='1, QSEND={2'b0,2'h0}, QOP={2'b0,2'h1}, QCL={2'b0,2'h2},
@@ -76,6 +83,9 @@ module t (/*AUTOARG*/);
       if (QACK     !=  4) $stop;
       if (QRSP     !=  5) $stop;
 
+      if ($size(array5) != 5) $stop;
+      if ($size(array5i) != 5) $stop;
+
       $write("*-* All Finished *-*\n");
       $finish;
    end