github/verilator
1
0
Fork 1
mirror of https://github.com/verilator/verilator.git synced 2025-01-09 08:07:46 +00:00
Code Issues Packages Projects Releases Wiki Activity

Tests: Merge from pattern branch.

Browse Source
This commit is contained in:
Wilson Snyder 2013-12-21 08:29:04 -05:00
parent bcefc17631
commit 8a708f52f7
4 changed files with 85 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
test_regress/t/t_array_packed_value_list.pl → test_regress/t/t_array_pattern_packed.pl
View File

@ -10,11 +10,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug355");
compile (
);
);
execute (
check_finished=>1,
);
check_finished=>1,
);
ok(1);
1;

28
test_regress/t/t_array_packed_value_list.v → test_regress/t/t_array_pattern_packed.v
View File

@ -10,6 +10,34 @@ module t (/*AUTOARG*/
input clk;
logic [1:0] [3:0] [3:0] array_simp; // big endian array
initial begin
array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0};
if (array_simp[0] !== 16'h3210) $stop;
// verilator lint_off WIDTH
array_simp[0] = '{ 3 ,2 ,1, 0 };
// verilator lint_on WIDTH
if (array_simp[0] !== 16'h3210) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
//if (array_simp[0] !== 16'h3210) $stop;
//array_simp[0] = '{ 1:4'd3, default:13};
//if (array_simp[0] !== 16'hDD3D) $stop;
array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }};
if (array_simp !== 32'h3210_1234) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
//array_simp <= '{2 { '{4 { 4'd3, 4'd2, 4'd1, 4'd0 }} } };
$write("*-* All Finished *-*\n");
$finish;
end
//====================
// parameters for array sizes
localparam WA = 4; // address dimension size
localparam WB = 4; // bit dimension size

20
test_regress/t/t_array_pattern_unpacked.pl Executable file
View File

@ -0,0 +1,20 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug355");
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

34
test_regress/t/t_array_pattern_unpacked.v Normal file
View File

@ -0,0 +1,34 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Iztok Jeras.
module t (/*AUTOARG*/);
logic [3:0] array_simp [1:0] [3:0]; // big endian array
initial begin
array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0};
if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'h3210) $stop;
// verilator lint_off WIDTH
array_simp[0] = '{ 3 ,2 ,1, 0 };
// verilator lint_on WIDTH
if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'h3210) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
//array_simp[0] = '{ 1:4'd3, default:13 };
//if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'hDD3D) $stop;
array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }};
if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 32'h3210_1234) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
//array_simp <= '{2{ '{4{ 4'd3, 4'd2, 4'd1, 4'd0 }} }};
$write("*-* All Finished *-*\n");
$finish;
end
endmodule