Fix interface parameters used in loop generate constructs (#4664) (#4665)

This commit is contained in:
Anthony Donlon 2023-11-04 17:19:35 +00:00 committed by GitHub
parent eace1d9c67
commit 88fcbf5f1d
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 100 additions and 0 deletions

View File

@ -1313,6 +1313,10 @@ class ParamVisitor final : public VNVisitor {
// so process here rather than at the generate to avoid iteration problems
UINFO(9, " BEGIN " << nodep << endl);
UINFO(9, " GENFOR " << forp << endl);
// Visit child nodes before unrolling
iterateAndNextNull(forp->initsp());
iterateAndNextNull(forp->condp());
iterateAndNextNull(forp->incsp());
V3Width::widthParamsEdit(forp); // Param typed widthing will NOT recurse the body
// Outer wrapper around generate used to hold genvar, and to ensure genvar
// doesn't conflict in V3LinkDot resolution with other genvars

View File

@ -0,0 +1,24 @@
-Info: t/t_interface_param_genblk.v:35:9: correct
: ... note: In instance 't.i_sub'
35 | $info("correct");
| ^~~~~
-Info: t/t_interface_param_genblk.v:44:13: i = 98, j = 2
: ... note: In instance 't.i_sub'
44 | $info("i = %0d, j = %0d", i, j);
| ^~~~~
-Info: t/t_interface_param_genblk.v:44:13: i = 98, j = 1
: ... note: In instance 't.i_sub'
44 | $info("i = %0d, j = %0d", i, j);
| ^~~~~
-Info: t/t_interface_param_genblk.v:44:13: i = 100, j = 2
: ... note: In instance 't.i_sub'
44 | $info("i = %0d, j = %0d", i, j);
| ^~~~~
-Info: t/t_interface_param_genblk.v:44:13: i = 100, j = 1
: ... note: In instance 't.i_sub'
44 | $info("i = %0d, j = %0d", i, j);
| ^~~~~
-Info: t/t_interface_param_genblk.v:50:26: correct
: ... note: In instance 't.i_sub'
50 | intf.B * 50: $info("correct");
| ^~~~~

View File

@ -0,0 +1,18 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(linter => 1);
lint(
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

View File

@ -0,0 +1,54 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Anthony Donlon.
// SPDX-License-Identifier: CC0-1.0
// See #4664
interface intf #(
parameter A = 10
);
localparam B = A / A + 1; // 2
logic [A/10-1:0] sig;
endinterface
module t;
intf #(
.A(100)
) intf();
sub i_sub (
.intf
);
endmodule
module sub (
intf intf
);
if (intf.A == 10) begin
$error("incorrect");
end else if (intf.A / intf.B == 50) begin
// end else if (intf.A / $bits(intf.sig) == 10) begin // TODO: support this
$info("correct");
end else begin
$error("incorrect");
end
for (genvar i = intf.A - 2; i < intf.A + 1; i += intf.B) begin
for (genvar j = intf.B; j > intf.A - 100; j--) begin
if (i < intf.A - 2) $error("error");
if (i > intf.A) $error("error");
$info("i = %0d, j = %0d", i, j);
end
end
case (intf.A)
10, intf.A - 10: $error("incorrect");
intf.B * 50: $info("correct");
30: $error("incorrect");
default: $error("incorrect");
endcase
endmodule