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Tests: Add elaboration info test.

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This commit is contained in:
Wilson Snyder 2019-08-04 21:31:06 -04:00
parent 429f463032
commit 88b87429dc
4 changed files with 9 additions and 4 deletions
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1
test_regress/t/t_assert_comp.v
View File

@ -6,6 +6,7 @@
module t (/*AUTOARG*/);
if (0) begin
$info("User compile-time info");
$warning("User compile-time warning");
$error("User compile-time error");
end

5
test_regress/t/t_assert_comp_bad.out Normal file
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@ -0,0 +1,5 @@
[0] -Info: t_assert_comp_bad.v:9: Assertion failed in top.t.genblk1: User compile-time info
[0] %Warning: t_assert_comp_bad.v:10: Assertion failed in top.t.genblk1: User compile-time warning
[0] %Error: t_assert_comp_bad.v:11: Assertion failed in top.t.genblk1: User compile-time error
%Error: t/t_assert_comp_bad.v:11: Verilog $stop
Aborting...

6
test_regress/t/t_assert_comp_bad.pl
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@ -12,15 +12,13 @@ scenarios(simulator => 1);
compile(
verilator_flags2 => ['--assert'],
nc_flags2 => ['+assert'],
vcs_flags2 => ['-assert svaext'],
);
execute(
check_finished => 0,
fails => 1,
expect =>
'.*%Warning: t_assert_comp_bad.v:\d+: Assertion failed in top.t.genblk1: User compile-time warning
.*%Error: t_assert_comp_bad.v:\d+: Assertion failed in top.t.genblk1: User compile-time error'
expect_filename => $Self->{golden_filename},
);
ok(1);

1
test_regress/t/t_assert_comp_bad.v
View File

@ -6,6 +6,7 @@
module t (/*AUTOARG*/);
if (1) begin
$info("User compile-time info");
$warning("User compile-time warning");
$error("User compile-time error");
end