From 888af29a72a9e9e2ef0058f832186503f7eed364 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 21 Sep 2024 20:27:55 -0400
Subject: [PATCH] Delay struct type determination until elaboration

---
 src/verilog.y                        |  2 +-
 test_regress/t/t_struct_type_bad.out |  4 ++++
 test_regress/t/t_struct_type_bad.py  | 16 ++++++++++++++++
 test_regress/t/t_struct_type_bad.v   | 16 ++++++++++++++++
 4 files changed, 37 insertions(+), 1 deletion(-)
 create mode 100644 test_regress/t/t_struct_type_bad.out
 create mode 100755 test_regress/t/t_struct_type_bad.py
 create mode 100644 test_regress/t/t_struct_type_bad.v

diff --git a/src/verilog.y b/src/verilog.y
index 52fe7b4bc..e4b561c15 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -2212,7 +2212,7 @@ data_typeVirtual<nodeDTypep>:           // ==IEEE: data_type after yVIRTUAL [ yI
         ;
 
 data_type_or_void<nodeDTypep>:  // ==IEEE: data_type_or_void
-                data_type                               { $$ = $1; }
+                data_typeAny                            { $$ = $1; }
         |       yVOID
                         { $$ = new AstBasicDType{$1, LOGIC_IMPLICIT};
                           BBUNSUP($1, "Unsupported: void (for tagged unions)"); }
diff --git a/test_regress/t/t_struct_type_bad.out b/test_regress/t/t_struct_type_bad.out
new file mode 100644
index 000000000..0e0aeda51
--- /dev/null
+++ b/test_regress/t/t_struct_type_bad.out
@@ -0,0 +1,4 @@
+%Error: t/t_struct_type_bad.v:13:7: Expecting a data type: 'i'
+   13 |       i badi;   
+      |       ^
+%Error: Exiting due to
diff --git a/test_regress/t/t_struct_type_bad.py b/test_regress/t/t_struct_type_bad.py
new file mode 100755
index 000000000..31228c9a7
--- /dev/null
+++ b/test_regress/t/t_struct_type_bad.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_struct_type_bad.v b/test_regress/t/t_struct_type_bad.v
new file mode 100644
index 000000000..8bda6e66d
--- /dev/null
+++ b/test_regress/t/t_struct_type_bad.v
@@ -0,0 +1,16 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2012 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+
+   int i;
+
+   typedef struct packed {
+      int i;
+      i badi;  // Bad
+   } struct_t;
+
+endmodule