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Fix dotted references into generate fors
git-svn-id: file://localhost/svn/verilator/trunk/verilator@840 77ca24e4-aefa-0310-84f0-b9a241c72d87
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@ -98,6 +98,12 @@ string AstNode::prettyName(const string& namein) {
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while ((pos=pretty.find("__DOT__")) != string::npos) {
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pretty.replace(pos, 7, ".");
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}
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while ((pos=pretty.find("__BRA__")) != string::npos) {
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pretty.replace(pos, 7, "[");
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}
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while ((pos=pretty.find("__KET__")) != string::npos) {
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pretty.replace(pos, 7, "]");
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}
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while ((pos=pretty.find("__PVT__")) != string::npos) {
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pretty.replace(pos, 7, "");
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}
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@ -90,7 +90,7 @@ public:
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string scopes;
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for (NameVtxMap::iterator it = m_nameToVtxMap.begin(); it!=m_nameToVtxMap.end(); ++it) {
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if (scopes != "") scopes += ", ";
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scopes += it->second->cellName();
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scopes += AstNode::prettyName(it->second->cellName());
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}
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cerr<<V3Error::msgPrefix()<<" Known scopes under '"<<cellName()<<"': "
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<<scopes<<endl;
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@ -145,6 +145,27 @@ public:
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virtual string dotColor() const { return "yellow"; }
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};
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class LinkDotBeginVertex : public LinkDotBaseVertex {
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// A fake point in the hierarchy, corresponding to a begin block
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// After we remove begins these will go away
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// Note we use the symbol table of the parent, as we want to find variables there
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// However, cells walk the graph, so cells will appear under the begin itself
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AstBegin* m_nodep; // Relevant node
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LinkDotCellVertex* m_symVxp; // Above cell so we can find real symbol table
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// // (Could walk graph to find it, but that's much slower.)
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public:
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LinkDotBeginVertex(V3Graph* graphp, AstBegin* nodep, LinkDotCellVertex* symVxp)
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: LinkDotBaseVertex(graphp, nodep->name()+"__DOT__")
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, m_nodep(nodep), m_symVxp(symVxp) {}
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virtual ~LinkDotBeginVertex() {}
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// Search up through tree to find the real symbol table.
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virtual V3SymTable& syms() { return m_symVxp->syms(); }
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virtual string modName() const { return m_nodep->name(); }
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virtual string cellName() const { return m_nodep->name(); }
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virtual string name() const { return (string)("BEG C:")+cellName(); }
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virtual string dotColor() const { return "blue"; }
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};
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//######################################################################
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// LinkDot state, as a visitor of each AstNode
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@ -214,6 +235,14 @@ public:
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}
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return vxp;
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}
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LinkDotBeginVertex* insertBegin(LinkDotBaseVertex* abovep, LinkDotCellVertex* cellVxp,
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AstBegin* nodep) {
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UINFO(9," INSERTbeg "<<nodep<<endl);
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LinkDotBeginVertex* vxp = new LinkDotBeginVertex(&m_graph, nodep, cellVxp);
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new V3GraphEdge(&m_graph, abovep, vxp, 1, false);
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abovep->insertSubcellName(nodep->name(), vxp);
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return vxp;
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}
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void insertSym(LinkDotCellVertex* abovep, const string& name, AstNode* nodep) {
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UINFO(9," INSERTsym "<<name<<" "<<nodep<<endl);
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abovep->syms().insert(name, nodep);
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@ -382,8 +411,9 @@ private:
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string oldscope = m_scope;
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AstBegin* oldbeginp = m_beginp;
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LinkDotCellVertex* oldVxp = m_cellVxp;
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LinkDotBaseVertex* oldInlineVxp = m_inlineVxp;
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// Where do we add it?
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LinkDotBaseVertex* aboveVxp = m_cellVxp;
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LinkDotBaseVertex* aboveVxp = m_inlineVxp;
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string origname = nodep->prettyName();
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string::size_type pos;
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if ((pos = origname.rfind(".")) != string::npos) {
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@ -404,7 +434,7 @@ private:
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m_scope = oldscope;
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m_beginp = oldbeginp;
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m_cellVxp = oldVxp;
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m_inlineVxp = m_cellVxp;
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m_inlineVxp = oldInlineVxp;
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}
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virtual void visit(AstCellInline* nodep, AstNUser*) {
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UINFO(5," CELLINLINE under "<<m_scope<<" is "<<nodep<<endl);
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@ -426,10 +456,16 @@ private:
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}
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virtual void visit(AstBegin* nodep, AstNUser*) {
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UINFO(5," "<<nodep<<endl);
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// We don't pickup variables, but do need to find cells
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AstBegin* oldbegin = m_beginp;
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m_beginp = nodep;
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nodep->iterateChildren(*this);
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LinkDotBaseVertex* oldVxp = m_inlineVxp;
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{
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m_beginp = nodep;
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// Ignore begin names
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m_inlineVxp = m_statep->insertBegin(m_inlineVxp, m_cellVxp, nodep);
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// We don't pickup variables, but do need to find cells
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nodep->iterateChildren(*this);
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}
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m_inlineVxp = oldVxp;
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m_beginp = oldbegin;
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}
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virtual void visit(AstVar* nodep, AstNUser*) {
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@ -346,6 +346,13 @@ private:
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// Rename it, as otherwise we may get a conflict
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// V3Begin sees these DOTs and makes CellInlines for us.
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string nname = (string)"genfor"+cvtToStr(m_varValuep->asInt())+"__DOT__"+nodep->name();
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if (nodep->name() != "genblk"
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&& nodep->name().find("__DOT__") == string::npos) {
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// Verilog seems to drop the for loop name and tack on [#]
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//nname = nodep->name() + "__BRA__" + cvtToStr(m_varValuep->asInt()) + "__KET__";
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// However we don't parse [#]'s correctly, so just use __ for now.
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nname = nodep->name() + "__" + cvtToStr(m_varValuep->asInt());
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}
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//UINFO(8," Rename begin "<<nname<<" "<<nodep<<endl);
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nodep->name(nname);
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}
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@ -38,6 +38,14 @@ module t (/*AUTOARG*/
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end
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end
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//`define WAVES
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`ifdef WAVES
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initial begin
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$dumpfile("obj_dir/t_gen_intdot.vcd");
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$dumpvars(12, t);
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end
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`endif
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endmodule
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module Generate (clk, value, result);
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@ -82,12 +90,22 @@ module Genit (clk, value, result);
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genvar i;
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generate
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for (i = 0; i < 1; i = i + 1)
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begin : gen
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Test t (clk, value, result);
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begin : foo
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Test tt (clk, value, result);
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end
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endgenerate
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`else
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Test t (clk, value, result);
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Test tt (clk, value, result);
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`endif
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`ifdef verilator
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wire Result2 = t.g.genblk.foo__0.tt.gen.Internal;
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`else
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wire Result2 = t.g.foo[0].tt.gen.Internal; // Works - Do not change!
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`endif
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always @ (posedge clk) begin
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$write("[%0t] Result2 = %x\n", $time, Result2);
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end
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endmodule
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