diff --git a/.github/workflows/coverage.yml b/.github/workflows/coverage.yml index 997a95e4b..5315418ef 100644 --- a/.github/workflows/coverage.yml +++ b/.github/workflows/coverage.yml @@ -102,4 +102,4 @@ jobs: CODECOV_TOKEN: ${{ secrets.CODECOV_TOKEN }} run: | find . -name '*.gcno' -exec rm {} \; - ./ci/codecov -v do-upload -Z --sha ${{ github.sha }} -f nodist/obj_dir/coverage/app_total.info + ./ci/codecov -v upload-process -Z --sha ${{ github.sha }} -f nodist/obj_dir/coverage/app_total.info diff --git a/nodist/code_coverage b/nodist/code_coverage index d0bb9ceba..00e3730bd 100755 --- a/nodist/code_coverage +++ b/nodist/code_coverage @@ -262,12 +262,21 @@ def cleanup_abs_paths_info(cc_dir, infile, outfile): lines = [] with open(infile, "r", encoding="utf8") as fh: for line in fh: - if re.search(r'^SF:', line): + if re.search(r'^SF:', line) and not re.search(r'^SF:/usr/', line): line = re.sub(os.environ['VERILATOR_ROOT'] + '/', '', line, count=1) line = re.sub(cc_dir + '/', '', line, count=1) + line = re.sub(r'^SF:.*?/include/', + 'SF:include/', + line, + count=1) + line = re.sub(r'^SF:.*?/src/', 'SF:src/', line, count=1) + line = re.sub(r'^SF:.*?/test_regress/', + 'SF:test_regress/', + line, + count=1) line = re.sub(r'obj_dbg/verilog.y$', 'verilog.y', line) # print("Remaining SF: "+line) lines.append(line) diff --git a/src/V3EmitCFunc.cpp b/src/V3EmitCFunc.cpp index b2b26c502..c601179a9 100644 --- a/src/V3EmitCFunc.cpp +++ b/src/V3EmitCFunc.cpp @@ -768,7 +768,7 @@ string EmitCFunc::emitVarResetRecurse(const AstVar* varp, const string& varNameP } return out; } - } else { + } else { // LCOV_EXCL_BR_LINE v3fatalSrc("Unknown node type in reset generator: " << varp->prettyTypeName()); } return ""; diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h index ea2e23482..722b63726 100644 --- a/src/V3EmitCFunc.h +++ b/src/V3EmitCFunc.h @@ -1481,15 +1481,13 @@ public: } // Default - void visit(AstNode* nodep) override { + void visit(AstNode* nodep) override { // LCOV_EXCL_START putns(nodep, "\n???? // "s + nodep->prettyTypeName() + "\n"); iterateChildrenConst(nodep); - // LCOV_EXCL_START if (!v3Global.opt.lintOnly()) { // An internal problem, so suppress nodep->v3fatalSrc("Unknown node type reached emitter: " << nodep->prettyTypeName()); } - // LCOV_EXCL_STOP - } + } // LCOV_EXCL_STOP EmitCFunc() : m_lazyDecls(*this) {} diff --git a/src/V3Number.cpp b/src/V3Number.cpp index 15cd9ffc2..58192c310 100644 --- a/src/V3Number.cpp +++ b/src/V3Number.cpp @@ -1202,16 +1202,6 @@ V3Number& V3Number::opBitsZ(const V3Number& lhs) { // 0/1->1, X/Z->0 } return *this; } -V3Number& V3Number::opBitsNonZ(const V3Number& lhs) { // 0/1->1, X/Z->0 - // op i, L(lhs) bit return - NUM_ASSERT_OP_ARGS1(lhs); - NUM_ASSERT_LOGIC_ARGS1(lhs); - setZero(); - for (int bit = 0; bit < width(); bit++) { - if (!lhs.bitIsZ(bit)) setBit(bit, 1); - } - return *this; -} //====================================================================== // Operators - Simple per-bit logical ops diff --git a/src/V3Number.h b/src/V3Number.h index 0b970b940..dd3653383 100644 --- a/src/V3Number.h +++ b/src/V3Number.h @@ -670,7 +670,6 @@ public: V3Number& opBitsOne(const V3Number& lhs); // 1->1, 0/X/Z->0 V3Number& opBitsXZ(const V3Number& lhs); // 0/1->0, X/Z->1 V3Number& opBitsZ(const V3Number& lhs); // Z->1, 0/1/X->0 - V3Number& opBitsNonZ(const V3Number& lhs); // Z->0, 0/1/X->1 // V3Number& opAssign(const V3Number& lhs); V3Number& opAssignNonXZ(const V3Number& lhs, bool ignoreXZ = true); diff --git a/src/V3Options.cpp b/src/V3Options.cpp index 576732d55..eb31d5502 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -707,9 +707,9 @@ string V3Options::getenvSYSTEMC_ARCH() { uname(&uts); const string sysname = VString::downcase(uts.sysname); // aka 'uname -s' if (VL_UNCOVERABLE(VString::wildmatch(sysname.c_str(), "*solaris*"))) { - var = "gccsparcOS5"; + var = "gccsparcOS5"; // LCOV_EXCL_LINE } else if (VL_UNCOVERABLE(VString::wildmatch(sysname.c_str(), "*cygwin*"))) { - var = "cygwin"; + var = "cygwin"; // LCOV_EXCL_LINE } else { var = "linux"; } diff --git a/src/V3ParseImp.cpp b/src/V3ParseImp.cpp index 2e2011c1c..e352ee5ac 100644 --- a/src/V3ParseImp.cpp +++ b/src/V3ParseImp.cpp @@ -404,9 +404,9 @@ size_t V3ParseImp::tokenPipeScanParam(size_t depth) { int parens = 1; // Count first ( while (true) { const int tok = tokenPeekp(depth)->token; - if (tok == 0) { + if (tok == 0) { // LCOV_EXCL_BR_LINE UINFO(9, "tokenPipeScanParam hit EOF; probably syntax error to come"); - break; + break; // LCOV_EXCL_LINE } else if (tok == '(') { ++parens; } else if (tok == ')') { @@ -430,9 +430,9 @@ size_t V3ParseImp::tokenPipeScanType(size_t depth) { int parens = 1; // Count first ( while (true) { const int tok = tokenPeekp(depth)->token; - if (tok == 0) { + if (tok == 0) { // LCOV_EXCL_BR_LINE UINFO(9, "tokenPipeScanType hit EOF; probably syntax error to come"); - break; + break; // LCOV_EXCL_LINE } else if (tok == '(') { ++parens; } else if (tok == ')') { diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp index 3457add27..86a748394 100644 --- a/src/V3PreProc.cpp +++ b/src/V3PreProc.cpp @@ -1254,10 +1254,10 @@ int V3PreProcImp::getStateToken() { static string newlines; newlines = "\n"; // Always start with trailing return if (tok == VP_DEFVALUE) { - if (debug() >= 5) { + if (debug() >= 5) { // LCOV_EXCL_START cout << "DefValue='" << V3PreLex::cleanDbgStrg(m_lexp->m_defValue) << "' formals='" << V3PreLex::cleanDbgStrg(m_formals) << "'\n"; - } + } // LCOV_EXCL_STOP // Add any formals const string formals = m_formals; string value = m_lexp->m_defValue; diff --git a/src/V3Simulate.h b/src/V3Simulate.h index 23d77b834..d9b950602 100644 --- a/src/V3Simulate.h +++ b/src/V3Simulate.h @@ -183,11 +183,11 @@ public: // and fetchConst should not be called or it may assert. if (!m_whyNotNodep) { m_whyNotNodep = nodep; - if (debug() >= 5) { + if (debug() >= 5) { // LCOV_EXCL_START UINFO(0, "Clear optimizable: " << why); if (nodep) std::cout << ": " << nodep; std::cout << std::endl; - } + } // LCOV_EXCL_STOP m_whyNotOptimizable = why; std::ostringstream stack; for (const auto& callstack : vlstd::reverse_view(m_callStack)) { diff --git a/src/V3SymTable.h b/src/V3SymTable.h index 836ee8e55..815356fa4 100644 --- a/src/V3SymTable.h +++ b/src/V3SymTable.h @@ -121,11 +121,12 @@ public: UINFO(9, " SymInsert se" << cvtToHex(this) << " '" << name << "' se" << cvtToHex(entp) << " " << entp->nodep() << endl); if (name != "" && m_idNameMap.find(name) != m_idNameMap.end()) { - if (!V3Error::errorCount()) { // Else may have just reported warning + // If didn't already report warning + if (!V3Error::errorCount()) { // LCOV_EXCL_START if (debug() >= 9 || V3Error::debugDefault()) dumpSelf(std::cout, "- err-dump: ", 1); entp->nodep()->v3fatalSrc("Inserting two symbols with same name: " << name); - } + } // LCOV_EXCL_STOP } else { m_idNameMap.emplace(name, entp); } diff --git a/src/V3Task.cpp b/src/V3Task.cpp index b59ca7065..0b88636b4 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -1020,7 +1020,7 @@ class TaskVisitor final : public VNVisitor { portp->v3warn( E_UNSUPPORTED, "Unsupported: DPI argument of type " - << portp->basicp()->prettyTypeName() << '\n' + << portp->dtypep()->prettyTypeName() << '\n' << portp->warnMore() << "... For best portability, use bit, byte, int, or longint"); // We don't warn on logic either, although the 4-stateness is lost. diff --git a/test_regress/t/t_debug_gate.pl b/test_regress/t/t_debug_gate.pl new file mode 100755 index 000000000..4867dec5d --- /dev/null +++ b/test_regress/t/t_debug_gate.pl @@ -0,0 +1,19 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +compile( + # Check we can call dump() on graph, and other things + v_flags => ["--debug --debugi 0 --debugi-V3Graph 9"], + ); + +ok(1); +1; diff --git a/test_regress/t/t_debug_gate.v b/test_regress/t/t_debug_gate.v new file mode 100644 index 000000000..865e3f8ea --- /dev/null +++ b/test_regress/t/t_debug_gate.v @@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Dotted reference that uses another dotted reference +// as the select expression +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Outputs + o, + // Inputs + i + ); + input i; + output o; + sub sub (.i, .o); +endmodule + +module sub(/*AUTOARG*/ + // Outputs + o, + // Inputs + i + ); + input i; + output o; + assign o = !i; +endmodule diff --git a/test_regress/t/t_debug_trace.pl b/test_regress/t/t_debug_trace.pl new file mode 100755 index 000000000..e68e695f7 --- /dev/null +++ b/test_regress/t/t_debug_trace.pl @@ -0,0 +1,19 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +compile( + # Check we can call dump() on graph, and other things + v_flags => ["--trace --debug --debugi 0 --debugi-V3Trace 9"], + ); + +ok(1); +1; diff --git a/test_regress/t/t_debug_trace.v b/test_regress/t/t_debug_trace.v new file mode 100644 index 000000000..36ce9c551 --- /dev/null +++ b/test_regress/t/t_debug_trace.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Dotted reference that uses another dotted reference +// as the select expression +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + a + ); + input a; + sub sub (); +endmodule + +module sub; + reg svar; +endmodule diff --git a/test_regress/t/t_display.out b/test_regress/t/t_display.out index 259cffc0f..0c5fe4274 100644 --- a/test_regress/t/t_display.out +++ b/test_regress/t/t_display.out @@ -88,11 +88,16 @@ multiline log10(2) = 2 x xxXa -XXX 1x5X +xxxX2 +XXX +Zx5X +zx5X x z X Z ZzX +ZzXx +XXXx 10 *-* All Finished *-* diff --git a/test_regress/t/t_display.v b/test_regress/t/t_display.v index 9e23bd3b6..2cf490fc2 100644 --- a/test_regress/t/t_display.v +++ b/test_regress/t/t_display.v @@ -200,12 +200,17 @@ multiline", $time); // unknown and high-impedance values $display("%d", 1'bx); $display("%h", 14'bx01010); - $display("%h %o", 12'b001xxx101x01, 12'b001xxx101x01); + $display("%o", 14'bx01010); + $display("%h", 12'b001x_xx10_1x01); + $display("%o", 12'bz01_xxx_101_x01); + $display("%o", 12'bzzz_xxx_101_x01); $display("%d", 32'bx); $display("%d", 32'bz); $display("%d", 32'b11x11z111); $display("%d", 32'b11111z111); $display("%h", 12'b1zz1_zzzz_1x1z); + $display("%o", 12'b1zz_zzz_x1x_xxx); + $display("%o", 12'b1zx_zzx_x1z_xxx); $display(,, 10); // Strange but legal diff --git a/test_regress/t/t_dpi_argtype_bad.out b/test_regress/t/t_dpi_argtype_bad.out new file mode 100644 index 000000000..6a7b7d9c2 --- /dev/null +++ b/test_regress/t/t_dpi_argtype_bad.out @@ -0,0 +1,7 @@ +%Error-UNSUPPORTED: t/t_dpi_argtype_bad.v:13:41: Unsupported: DPI argument of type REFDTYPE 'foo_t' + : ... For best portability, use bit, byte, int, or longint + 13 | import "DPI-C" task dpix_twice(foo_t arg); + | ^~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Verilator internal fault, sorry. Suggest trying --debug --gdbbt +%Error: Command Failed diff --git a/test_regress/t/t_dpi_argtype_bad.pl b/test_regress/t/t_dpi_argtype_bad.pl new file mode 100755 index 000000000..59ba0d6c6 --- /dev/null +++ b/test_regress/t/t_dpi_argtype_bad.pl @@ -0,0 +1,19 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +lint( + fails => $Self->{vlt_all}, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_dpi_argtype_bad.v b/test_regress/t/t_dpi_argtype_bad.v new file mode 100644 index 000000000..b6b18e608 --- /dev/null +++ b/test_regress/t/t_dpi_argtype_bad.v @@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2021 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +module t; + + typedef struct { string a; string b; } foo_t; + + import "DPI-C" task dpix_twice(foo_t arg); + initial begin + $stop; + end +endmodule diff --git a/test_regress/t/t_enum_public.v b/test_regress/t/t_enum_public.v index 4fcf012ff..3944190bd 100644 --- a/test_regress/t/t_enum_public.v +++ b/test_regress/t/t_enum_public.v @@ -19,6 +19,11 @@ package p62; ALLONE = '1 } e62_t /*verilator public*/; endpackage +package pw; + typedef enum logic [99:0] { // Too wide for public + WIDE = 100'h123} ewide_t /*verilator public*/; +endpackage + module t (/*AUTOARG*/); enum integer { diff --git a/test_regress/t/t_langext_2012ext.pl b/test_regress/t/t_langext_2012ext.pl new file mode 100755 index 000000000..cbf040cde --- /dev/null +++ b/test_regress/t/t_langext_2012ext.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +top_filename("t/t_langext_2.v"); + +# This is a compile only test. +compile( + v_flags2 => ["+1800-2012ext+v"], + ); + +ok(1); +1; diff --git a/test_regress/t/t_langext_2017ext.pl b/test_regress/t/t_langext_2017ext.pl new file mode 100755 index 000000000..7aa0a8c5f --- /dev/null +++ b/test_regress/t/t_langext_2017ext.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +top_filename("t/t_langext_2.v"); + +# This is a compile only test. +compile( + v_flags2 => ["+1800-2017ext+v"], + ); + +ok(1); +1; diff --git a/test_regress/t/t_langext_2023ext.pl b/test_regress/t/t_langext_2023ext.pl new file mode 100755 index 000000000..6badad6e3 --- /dev/null +++ b/test_regress/t/t_langext_2023ext.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +top_filename("t/t_langext_2.v"); + +# This is a compile only test. +compile( + v_flags2 => ["+1800-2023ext+v"], + ); + +ok(1); +1; diff --git a/test_regress/t/t_lint_pragma_protected_bad.out b/test_regress/t/t_lint_pragma_protected_bad.out index dac9a4676..3b50e2c31 100644 --- a/test_regress/t/t_lint_pragma_protected_bad.out +++ b/test_regress/t/t_lint_pragma_protected_bad.out @@ -47,7 +47,34 @@ %Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:74:17: A '`pragma protected data_block' encrypted section was detected and will be skipped. %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:75:1: BASE64 line too long in `pragma protect key_bloock/data_block %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:75:1: BASE64 encoding length mismatch in `pragma protect key_bloock/data_block -%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:83:1: `pragma is missing a pragma_expression. - 83 | `pragma +%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:77:17: Multiple `pragma protected encoding sections + 77 | `pragma protect encoding = (enctype = "UUENCODE", line_length = 1, bytes = 4) + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_lint_pragma_protected_bad.v:77:17: Unsupported: only BASE64 is recognized for `pragma protected encoding + 77 | `pragma protect encoding = (enctype = "UUENCODE", line_length = 1, bytes = 4) + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:79:17: A '`pragma protected data_block' encrypted section was detected and will be skipped. +%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:80:1: BASE64 line too long in `pragma protect key_bloock/data_block +%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:80:1: BASE64 encoding length mismatch in `pragma protect key_bloock/data_block +%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:81:17: Multiple `pragma protected encoding sections + 81 | `pragma protect encoding = (enctype = "QUOTED-PRINTABLE", line_length = 1, bytes = 4) + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:81:17: Illegal encoding type for `pragma protected encoding + 81 | `pragma protect encoding = (enctype = "QUOTED-PRINTABLE", line_length = 1, bytes = 4) + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_lint_pragma_protected_bad.v:81:17: Unsupported: only BASE64 is recognized for `pragma protected encoding + 81 | `pragma protect encoding = (enctype = "QUOTED-PRINTABLE", line_length = 1, bytes = 4) + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:83:17: A '`pragma protected data_block' encrypted section was detected and will be skipped. +%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:84:1: BASE64 encoding (too short) in `pragma protect key_bloock/data_block +%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:84:1: BASE64 encoding length mismatch in `pragma protect key_bloock/data_block +%Error-UNSUPPORTED: t/t_lint_pragma_protected_bad.v:85:17: Unsupported: only BASE64 is recognized for `pragma protected encoding + 85 | `pragma protect encoding = (enctype = "RAW", line_length = 1, bytes = 4) + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:87:17: A '`pragma protected data_block' encrypted section was detected and will be skipped. +%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:88:1: BASE64 line too long in `pragma protect key_bloock/data_block +%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:88:1: BASE64 encoding length mismatch in `pragma protect key_bloock/data_block +%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:96:1: `pragma is missing a pragma_expression. + 96 | `pragma | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_pragma_protected_bad.v b/test_regress/t/t_lint_pragma_protected_bad.v index 68e3c159d..c2488b2b7 100644 --- a/test_regress/t/t_lint_pragma_protected_bad.v +++ b/test_regress/t/t_lint_pragma_protected_bad.v @@ -74,6 +74,19 @@ aW5pdGlvbnMuCgogIEFzIHVzZWQgaGVyZWluLCAidGhpcyBMaWNlbnNlIiByZWZlcnMgdG8gdmVyTOOL aW5p +`pragma protect encoding = (enctype = "UUENCODE", line_length = 1, bytes = 4) +`pragma protect data_block +aW5p + +`pragma protect encoding = (enctype = "QUOTED-PRINTABLE", line_length = 1, bytes = 4) +`pragma protect data_block +aW5p + +`pragma protect encoding = (enctype = "RAW", line_length = 1, bytes = 4) +`pragma protect data_block +aW5p + + `pragma protect end_protected // Should trigger unknown pragma warning, although in principle unknown pragmas should be safely ignored. diff --git a/test_regress/t/t_pp_underline_bad.out b/test_regress/t/t_pp_underline_bad.out index d2bd08689..1803a72b6 100644 --- a/test_regress/t/t_pp_underline_bad.out +++ b/test_regress/t/t_pp_underline_bad.out @@ -1,6 +1,9 @@ %Error: t/t_pp_underline_bad.v:8:4: Extra underscore in meta-comment; use /*verilator {...}*/ not /*verilator_{...}*/ 8 | // verilator_no_inline_module | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: t/t_pp_underline_bad.v:10:19: Extra underscore in meta-comment; use /*synopsys {...}*/ not /*synopsys_{...}*/ + 10 | case (1'b1) // synopsys_full_case + | ^~~~~~~~~~~~~~~~~~~~~ %Error: t/t_pp_underline_bad.v:8:4: Unknown verilator comment: '/*verilator _no_inline_module*/' 8 | /*verilator _no_inline_module*/ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/test_regress/t/t_pp_underline_bad.v b/test_regress/t/t_pp_underline_bad.v index 63f0c9c47..adcd87d58 100644 --- a/test_regress/t/t_pp_underline_bad.v +++ b/test_regress/t/t_pp_underline_bad.v @@ -6,5 +6,10 @@ module t; // verilator_no_inline_module - initial $stop; // Should have failed + initial begin + case (1'b1) // synopsys_full_case + endcase + $stop; // Should have failed + end + endmodule diff --git a/test_regress/t/t_udp.v b/test_regress/t/t_udp.v index 26eb1104d..c282b63a4 100644 --- a/test_regress/t/t_udp.v +++ b/test_regress/t/t_udp.v @@ -108,7 +108,11 @@ primitive udp_mux2 (z, a, b, sel); 1 ? 0 : 1 ; 0 ? 0 : 0 ; 1 1 x : 1 ; - 0 0 x : 0 ; + // Next blank line is intentional for parser + + // Next \ at EOL is intentional for parser + 0 0 x \ + : 0 ; endtable endprimitive diff --git a/test_regress/t/t_vams_basic.v b/test_regress/t/t_vams_basic.v index 8a71bfe42..5b567f738 100644 --- a/test_regress/t/t_vams_basic.v +++ b/test_regress/t/t_vams_basic.v @@ -27,6 +27,8 @@ module t (/*AUTOARG*/ sub sub (.*); initial begin + check(`__LINE__, asin(0.5) , 0.523599); + check(`__LINE__, asinh(0.5) , 0.481212); check(`__LINE__, atan(0.5) , 0.463648); check(`__LINE__, atan2(0.5, 0.3) , 1.03038); check(`__LINE__, atanh(0.5) , 0.549306); diff --git a/test_regress/t/t_wire_triand.out b/test_regress/t/t_wire_triand.out new file mode 100644 index 000000000..c64acb3a9 --- /dev/null +++ b/test_regress/t/t_wire_triand.out @@ -0,0 +1,8 @@ +%Error-UNSUPPORTED: t/t_wire_triand.v:11:4: Unsupported: triand + 11 | triand ta; + | ^~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_wire_triand.v:12:4: Unsupported: trior + 12 | trior to; + | ^~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_wire_triand.pl b/test_regress/t/t_wire_triand.pl new file mode 100755 index 000000000..59ba0d6c6 --- /dev/null +++ b/test_regress/t/t_wire_triand.pl @@ -0,0 +1,19 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +lint( + fails => $Self->{vlt_all}, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_wire_triand.v b/test_regress/t/t_wire_triand.v new file mode 100644 index 000000000..dcd94f310 --- /dev/null +++ b/test_regress/t/t_wire_triand.v @@ -0,0 +1,14 @@ +// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' +// +// Simple bi-directional alias test. +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + + triand ta; + trior to; + +endmodule