github/verilator
1
0
Fork 1
mirror of https://github.com/verilator/verilator.git synced 2025-01-05 22:27:35 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fix display constanting of neg quads. Part of previous checkin

Browse Source 
git-svn-id: file://localhost/svn/verilator/trunk/verilator@939 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2007-06-14 21:27:40 +00:00
parent d6a5c97f3a
commit 829d80d5b5
4 changed files with 45 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/V3Number.cpp
View File

@ -464,11 +464,10 @@ vluint64_t V3Number::asQuad() const {
}
vlsint64_t V3Number::asSQuad() const {
if (width()<=32) return ((vlsint64_t)(asSInt()));
vluint64_t v = asQuad();
vluint64_t signExtend = (-(v & (1UL<<(width()-1))));
vluint64_t signExtend = (-(v & (VL_ULL(1)<<(width()-1))));
vluint64_t extended = v | signExtend;
return (vlsint32_t)(extended);
return (vlsint64_t)(extended);
}
uint32_t V3Number::asHash() const {

12
test_regress/t/t_display_signed.pl
View File

@ -13,12 +13,12 @@ compile (
execute (
check_finished=>1,
expect=> quotemeta(
'[0] %x=0bbccc %x=0bbccc %o=2736314 %b=010111011110011001100 %0d=769228 %d= 769228
[0] %x=1bbccc %x=1bbccc %o=6736314 %b=110111011110011001100 %0d=-279348 %d= -279348
[0] %x=000bbbbcccc %x=000bbbbcccc %o=00027356746314 %b=00000000010111011101110111100110011001100 %0d=3149647052 %d= 3149647052
[0] %x=100bbbbcccc %x=100bbbbcccc %o=20027356746314 %b=10000000010111011101110111100110011001100 %0d=-1096361980724 %d=-1096361980724
[0] %x=000bc1234567812345678 %x=000bc1234567812345678 %o=000570110642547402215053170 %b=000000000101111000001001000110100010101100111100000010010001101000101011001111000
[0] %x=000bc1234577812345678 %x=000bc1234577812345678 %o=000570110642567402215053170 %b=000000000101111000001001000110100010101110111100000010010001101000101011001111000
'[0] lp %x=0bbccc %x=0bbccc %o=2736314 %b=010111011110011001100 %0d=769228 %d= 769228
[0] ln %x=1bbccc %x=1bbccc %o=6736314 %b=110111011110011001100 %0d=-279348 %d= -279348
[0] qp %x=001bbbbcccc %x=001bbbbcccc %o=00067356746314 %b=00000000110111011101110111100110011001100 %0d=7444614348 %d= 7444614348
[0] qn %x=101bbbbcccc %x=101bbbbcccc %o=20067356746314 %b=10000000110111011101110111100110011001100 %0d=-1092067013428 %d=-1092067013428
[0] wp %x=000bc1234567812345678 %x=000bc1234567812345678 %o=000570110642547402215053170 %b=000000000101111000001001000110100010101100111100000010010001101000101011001111000
[0] wn %x=000bc1234577812345678 %x=000bc1234577812345678 %o=000570110642567402215053170 %b=000000000101111000001001000110100010101110111100000010010001101000101011001111000
'),
);

16
test_regress/t/t_display_signed.v
View File

@ -7,24 +7,24 @@
module t;
reg signed [20:0] longp; initial longp = 21'shbbccc;
reg signed [20:0] longn; initial longn = 21'shbbccc; initial longn[20]=1'b1;
reg signed [40:0] quadp; initial quadp = 41'shbbbb_cccc;
reg signed [40:0] quadn; initial quadn = 41'shbbbb_cccc; initial quadn[40]=1'b1;
reg signed [40:0] quadp; initial quadp = 41'sh1_bbbb_cccc;
reg signed [40:0] quadn; initial quadn = 41'sh1_bbbb_cccc; initial quadn[40]=1'b1;
reg signed [80:0] widep; initial widep = 81'shbc_1234_5678_1234_5678;
reg signed [80:0] widen; initial widen = 81'shbc_1234_5678_1234_5678; initial widen[40]=1'b1;
initial begin
// Display formatting
$display("[%0t] %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
$display("[%0t] lp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
longp, longp, longp, longp, longp, longp);
$display("[%0t] %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
$display("[%0t] ln %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
longn, longn, longn, longn, longn, longn);
$display("[%0t] %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
$display("[%0t] qp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
quadp, quadp, quadp, quadp, quadp, quadp);
$display("[%0t] %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
$display("[%0t] qn %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
quadn, quadn, quadn, quadn, quadn, quadn);
$display("[%0t] %%x=%x %%x=%x %%o=%o %%b=%b", $time,
$display("[%0t] wp %%x=%x %%x=%x %%o=%o %%b=%b", $time,
widep, widep, widep, widep);
$display("[%0t] %%x=%x %%x=%x %%o=%o %%b=%b", $time,
$display("[%0t] wn %%x=%x %%x=%x %%o=%o %%b=%b", $time,
widen, widen, widen, widen);
$display;
$write("*-* All Finished *-*\n");

29
test_regress/t/t_display_signed_noopt.pl Executable file
View File

@ -0,0 +1,29 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# $Id$
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# General Public License or the Perl Artistic License.
top_filename("t/t_display_signed.v");
compile (
v_flags2 => [$Last_Self->{v3}?"-O0":""],
);
execute (
check_finished=>1,
expect=> quotemeta(
'[0] lp %x=0bbccc %x=0bbccc %o=2736314 %b=010111011110011001100 %0d=769228 %d= 769228
[0] ln %x=1bbccc %x=1bbccc %o=6736314 %b=110111011110011001100 %0d=-279348 %d= -279348
[0] qp %x=001bbbbcccc %x=001bbbbcccc %o=00067356746314 %b=00000000110111011101110111100110011001100 %0d=7444614348 %d= 7444614348
[0] qn %x=101bbbbcccc %x=101bbbbcccc %o=20067356746314 %b=10000000110111011101110111100110011001100 %0d=-1092067013428 %d=-1092067013428
[0] wp %x=000bc1234567812345678 %x=000bc1234567812345678 %o=000570110642547402215053170 %b=000000000101111000001001000110100010101100111100000010010001101000101011001111000
[0] wn %x=000bc1234577812345678 %x=000bc1234577812345678 %o=000570110642567402215053170 %b=000000000101111000001001000110100010101110111100000010010001101000101011001111000
'),
);
ok(1);
1;