Tests: Add t_param_array3 test, bug1315

test_regress/t/t_param_array3.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt_all} and unsupported("Verilator unsupported, bug1315 unpacked array parameter simulation");
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_param_array3.v

@@ -0,0 +1,30 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2018 by Wilson Snyder.
+
+module t;
+   parameter int SIZES [3:0] = '{1,2,3,4};
+   typedef int calc_sums_t [3:0];
+
+   function calc_sums_t calc_sums;
+      int sum = 0;
+      for (int i=0; i<4; i++) begin
+         sum = sum + SIZES[i];
+         calc_sums[i][31:0] = sum;
+      end
+   endfunction
+
+   parameter int SUMS[3:0] = calc_sums();
+
+   initial begin
+      $display("%d ",SUMS[0]);
+      if (SUMS[0] != 4) $stop;
+      if (SUMS[1] != 4+3) $stop;
+      if (SUMS[2] != 4+3+2) $stop;
+      if (SUMS[3] != 4+3+2+1) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule