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Tests: Test for bug1593.

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This commit is contained in:
Wilson Snyder 2019-11-07 18:15:55 -05:00
parent f1b10e2b4c
commit 8043a9c666
6 changed files with 55 additions and 2 deletions
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4
docs/internals.adoc
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@ -916,6 +916,10 @@ what made a <e####> line in the tree dumps):
watch AstNode::s_editCntGbl==####
Then, when the watch fires, to break at every following change to that node:
watch m_editCount
To print a node:
pn nodep

5
test_regress/driver.pl
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@ -366,7 +366,8 @@ sub wait_and_report {
# Wait for all children to finish
while ($::Fork->is_any_left) {
$::Fork->poll;
if (time() - ($self->{_last_summary_time} || 0) >= 30) {
if ((time() - ($self->{_last_summary_time} || 0) >= 30)
&& (!$opt_gdb && !$opt_gdbsim)) { # Don't show for interactive gdb etc
$self->print_summary(force=>1, show_running=>1);
}
Time::HiRes::usleep 100*1000;
@ -407,7 +408,7 @@ sub print_summary {
@_);
if (!$self->{quiet} || $params{force}
|| ($self->{left_cnt} < 5)
|| time() - ($self->{_last_summary_time} || 0) >= 15) {
|| (time() - ($self->{_last_summary_time} || 0) >= 15)) { # Don't show for interactive gdb etc
$self->{_last_summary_time} = time();
print STDERR ("==SUMMARY: ".$self->sprint_summary."\n");
if ($params{show_running}) {

5
test_regress/t/t_interface_param_acc_bits.out Normal file
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@ -0,0 +1,5 @@
%Error: t/t_interface_param_acc_bits.v:14: Parameter-resolved constants must not use dotted references: 'dummy'
: ... In instance t
simple_bus #(.PARAMETER($bits(sb_intf.dummy))) simple();
^~~~~
%Error: Exiting due to

18
test_regress/t/t_interface_param_acc_bits.pl Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
scenarios(simulator => 1);
compile(
fails => ($Self->{vlt} || $Self->{vltmt}), # Unsupported bug1523
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

20
test_regress/t/t_interface_param_acc_bits.v Normal file
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@ -0,0 +1,20 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Johan Bjork.
// bug1593
interface simple_bus #(PARAMETER = 0);
parameter [6:0] dummy = 22;
endinterface
module t ();
simple_bus sb_intf();
simple_bus #(.PARAMETER($bits(sb_intf.dummy))) simple();
initial begin
if (simple.PARAMETER != 7) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

5
test_regress/t/t_interface_parameter_access.v
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@ -41,12 +41,17 @@ module t (/*AUTOARG*/
);
localparam THE_TOP_FOO = the_interface.FOO;
localparam THE_TOP_FOO_BITS = $bits({the_interface.FOO, the_interface.FOO});
initial begin
if (THE_TOP_FOO != 5) begin
$display("%%Error: THE_TOP_FOO = %0d", THE_TOP_FOO);
$stop;
end
if (THE_TOP_FOO_BITS != 64) begin
$display("%%Error: THE_TOP_FOO_BITS = %0d", THE_TOP_FOO_BITS);
$stop;
end
end
endmodule