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Fix dotted reference in delay value (#2410).
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Wilson Snyder
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@ -21,6 +21,7 @@ Verilator 5.031 devel
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* Add error when improperly storing to parameter (#5147). [Gökçe Aydos]
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* Add coverage point hierarchy to coverage reports (#5575) (#5576). [Andrew Nolte]
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* Add error on `solve before` or soft constraints of `randc` variable.
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* Fix dotted reference in delay value (#2410).
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* Fix can't locate scope error in interface task delayed assignment (#5462) (#5568). [Zhou Shen]
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* Fix BLKANDNBLK for for VARXREFs (#5569). [Todd Strader]
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* Fix VPI error instead of fatal for vpi_get_value() on large signals (#5571). [Todd Strader]
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@ -3075,7 +3075,7 @@ delay_control<delayp>: //== IEEE: delay_control
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delay_value<nodeExprp>: // ==IEEE:delay_value
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// // IEEE: ps_identifier
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packageClassScopeE varRefBase { $$ = AstDot::newIfPkg($<fl>2, $1, $2); }
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idClass { $$ = $1; }
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| yaINTNUM { $$ = new AstConst{$<fl>1, *$1}; }
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| yaFLOATNUM { $$ = new AstConst{$<fl>1, AstConst::RealDouble{}, $1}; }
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| timeNumAdjusted { $$ = $1; }
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@ -5810,7 +5810,7 @@ idSVKwd<strp>: // Warn about non-forward compatible Verilog 200
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{ static string s = "final"; $$ = &s; ERRSVKWD($1, *$$); $<fl>$ = $<fl>1; }
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;
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variable_lvalue<nodeExprp>: // IEEE: variable_lvalue or net_lvalue
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variable_lvalue<nodeExprp>: // IEEE: variable_lvalue or net_lvalue
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// // Note many variable_lvalue's must use exprOkLvalue when arbitrary expressions may also exist
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idClassSel { $$ = $1; }
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| '{' variable_lvalueConcList '}' { $$ = $2; }
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@ -5832,8 +5832,19 @@ variable_lvalueConcList<nodeExprp>: // IEEE: part of variable_lvalue: '{' variab
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//UNSUP | variable_lvalueList ',' variable_lvalue { $$ = addNextNull($1, $3); }
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//UNSUP ;
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// VarRef to dotted, and/or arrayed, and/or bit-ranged variable
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idClassSel<nodeExprp>: // Misc Ref to dotted, and/or arrayed, and/or bit-ranged variable
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idClass<nodeExprp>: // Misc Ref to dotted, and/or arrayed, and/or bit-ranged variable
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idDotted { $$ = $1; }
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// // IEEE: [ implicit_class_handle . | package_scope ] hierarchical_variable_identifier select
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| yTHIS '.' idDotted
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{ $$ = new AstDot{$2, false, new AstParseRef{$<fl>1, VParseRefExp::PX_ROOT, "this"}, $3}; }
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| ySUPER '.' idDotted
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{ $$ = new AstDot{$2, false, new AstParseRef{$<fl>1, VParseRefExp::PX_ROOT, "super"}, $3}; }
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| yTHIS '.' ySUPER '.' idDotted { $$ = $5; BBUNSUP($1, "Unsupported: this.super"); }
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// // Expanded: package_scope idDottedSel
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| packageClassScope idDotted { $$ = new AstDot{$<fl>2, true, $1, $2}; }
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;
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idClassSel<nodeExprp>: // Misc Ref to dotted, and/or arrayed, and/or bit-ranged variable
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idDottedSel { $$ = $1; }
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// // IEEE: [ implicit_class_handle . | package_scope ] hierarchical_variable_identifier select
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| yTHIS '.' idDottedSel
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@ -5857,6 +5868,12 @@ idClassSelForeach<nodeExprp>:
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| packageClassScope idDottedForeach { $$ = new AstDot{$<fl>2, true, $1, $2}; }
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;
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idDotted<nodeExprp>:
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yD_ROOT '.' idDottedMore
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{ $$ = new AstDot{$2, false, new AstParseRef{$<fl>1, VParseRefExp::PX_ROOT, "$root"}, $3}; }
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| idDottedMore { $$ = $1; }
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;
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idDottedSel<nodeExprp>:
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yD_ROOT '.' idDottedSelMore
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{ $$ = new AstDot{$2, false, new AstParseRef{$<fl>1, VParseRefExp::PX_ROOT, "$root"}, $3}; }
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@ -5869,6 +5886,11 @@ idDottedForeach<nodeExprp>:
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| idDottedMoreForeach { $$ = $1; }
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;
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idDottedMore<nodeExprp>:
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varRefBase { $$ = $1; }
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| idDottedMore '.' varRefBase { $$ = new AstDot{$2, false, $1, $3}; }
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;
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idDottedSelMore<nodeExprp>:
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idArrayed { $$ = $1; }
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| idDottedSelMore '.' idArrayed { $$ = new AstDot{$2, false, $1, $3}; }
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@ -18,12 +18,14 @@ module t (/*AUTOARG*/
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wire [31:0] dly1;
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wire [31:0] dly2 = dly1 + 32'h1;
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wire [31:0] dly3;
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wire [31:0] dly4;
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typedef struct packed { int dly; } dly_s_t;
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dly_s_t dly_s;
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assign #(1.2000000000000000) dly1 = dly0 + 32'h1;
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assign #(sub.delay) dly3 = dly1 + 1;
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assign #sub.delay dly4 = dly1 + 1;
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sub sub();
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@ -1,39 +1,47 @@
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%Warning-ASSIGNDLY: t/t_delay.v:25:11: Ignoring timing control on this assignment/primitive due to --no-timing
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%Warning-ASSIGNDLY: t/t_delay.v:26:11: Ignoring timing control on this assignment/primitive due to --no-timing
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: ... note: In instance 't'
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25 | assign #(1.2000000000000000) dly1 = dly0 + 32'h1;
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26 | assign #(1.2000000000000000) dly1 = dly0 + 32'h1;
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| ^
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... For warning description see https://verilator.org/warn/ASSIGNDLY?v=latest
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... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message.
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%Warning-ASSIGNDLY: t/t_delay.v:26:11: Ignoring timing control on this assignment/primitive due to --no-timing
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%Warning-ASSIGNDLY: t/t_delay.v:27:11: Ignoring timing control on this assignment/primitive due to --no-timing
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: ... note: In instance 't'
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26 | assign #(sub.delay) dly3 = dly1 + 1;
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27 | assign #(sub.delay) dly3 = dly1 + 1;
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| ^
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%Warning-ASSIGNDLY: t/t_delay.v:33:18: Ignoring timing control on this assignment/primitive due to --no-timing
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%Warning-ASSIGNDLY: t/t_delay.v:28:11: Ignoring timing control on this assignment/primitive due to --no-timing
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: ... note: In instance 't'
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33 | dly0 <= #0 32'h11;
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| ^
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%Warning-ASSIGNDLY: t/t_delay.v:36:18: Ignoring timing control on this assignment/primitive due to --no-timing
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28 | assign #sub.delay dly4 = dly1 + 1;
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| ^
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%Warning-ASSIGNDLY: t/t_delay.v:35:18: Ignoring timing control on this assignment/primitive due to --no-timing
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: ... note: In instance 't'
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36 | dly0 <= #0.12 dly0 + 32'h12;
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35 | dly0 <= #0 32'h11;
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| ^
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%Warning-ASSIGNDLY: t/t_delay.v:44:18: Ignoring timing control on this assignment/primitive due to --no-timing
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%Warning-ASSIGNDLY: t/t_delay.v:38:18: Ignoring timing control on this assignment/primitive due to --no-timing
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: ... note: In instance 't'
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44 | dly0 <= #(dly_s.dly) 32'h55;
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38 | dly0 <= #0.12 dly0 + 32'h12;
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| ^
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%Warning-STMTDLY: t/t_delay.v:50:10: Ignoring delay on this statement due to --no-timing
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%Warning-ASSIGNDLY: t/t_delay.v:46:18: Ignoring timing control on this assignment/primitive due to --no-timing
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: ... note: In instance 't'
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46 | dly0 <= #(dly_s.dly) 32'h55;
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| ^
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%Warning-STMTDLY: t/t_delay.v:52:10: Ignoring delay on this statement due to --no-timing
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: ... note: In instance 't'
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50 | #100 $finish;
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52 | #100 $finish;
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| ^
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%Warning-UNUSEDSIGNAL: t/t_delay.v:23:12: Signal is not used: 'dly_s'
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%Warning-UNUSEDSIGNAL: t/t_delay.v:21:16: Signal is not used: 'dly4'
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: ... note: In instance 't'
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23 | dly_s_t dly_s;
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21 | wire [31:0] dly4;
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| ^~~~
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%Warning-UNUSEDSIGNAL: t/t_delay.v:24:12: Signal is not used: 'dly_s'
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: ... note: In instance 't'
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24 | dly_s_t dly_s;
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| ^~~~~
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%Warning-UNUSEDSIGNAL: t/t_delay.v:57:13: Signal is not used: 'delay'
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%Warning-UNUSEDSIGNAL: t/t_delay.v:59:13: Signal is not used: 'delay'
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: ... note: In instance 't.sub'
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57 | realtime delay = 2.3;
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59 | realtime delay = 2.3;
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| ^~~~~
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%Warning-BLKSEQ: t/t_delay.v:43:20: Blocking assignment '=' in sequential logic process
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%Warning-BLKSEQ: t/t_delay.v:45:20: Blocking assignment '=' in sequential logic process
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: ... Suggest using delayed assignment '<='
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43 | dly_s.dly = 55;
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45 | dly_s.dly = 55;
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| ^
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%Error: Exiting due to
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