Fix instance arrays connecting to array of structs (#4557).

Changes

@@ -37,6 +37,7 @@ Verilator 5.017 devel
 * Fix object destruction after a copy constructor (#4540) (#4541). [Ryszard Rozak, Antmicro Ltd.]
 * Fix inlining of real functions miscasting (#4543). [Andrew Nolte]
 * Fix broken link error for enum references (#4551). [Anthony Donlon]
+* Fix instance arrays connecting to array of structs (#4557). [raphmaster]
 * Fix preprocessor to show `line 2 on resumed file.
 
 

src/V3Inst.cpp

@@ -326,10 +326,10 @@ private:
                 = nodep->exprp()->dtypep()->dimensions(false);
             UINFO(4, "   PINVAR  " << nodep->modVarp() << endl);
             UINFO(4, "   EXP     " << nodep->exprp() << endl);
-            UINFO(4, "   modwidth ew=" << expwidth << " pw=" << modwidth << "  ed=" << expDim.first
-                                       << "," << expDim.second << "  pd=" << pinDim.first << ","
+            UINFO(4, "   expwidth=" << expwidth << " modwidth=" << modwidth << "  expDim(p,u)=" << expDim.first
+                                       << "," << expDim.second << "  pinDim(p,u)=" << pinDim.first << ","
                                        << pinDim.second << endl);
-            if (expDim.first == pinDim.first && expDim.second == pinDim.second + 1) {
+            if (expDim.second == pinDim.second + 1) {
                 // Connection to array, where array dimensions match the instant dimension
                 const AstRange* const rangep
                     = VN_AS(nodep->exprp()->dtypep(), UnpackArrayDType)->rangep();

test_regress/t/t_inst_array_struct.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_inst_array_struct.v

@@ -0,0 +1,48 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   typedef struct packed {
+      bit         one;
+      bit         two;
+   } ps_t;
+
+   ps_t in0 [2];
+   ps_t out0 [2];
+
+   bit [1:0] in1 [2] = {{1'b1, 1'b0}, {1'b0, 1'b1}};
+   bit [1:0] out1 [2];
+
+   Sub sub0 [2] (in0, out0);
+   Sub sub1 [2] (in1, out1);
+
+   int       cyc;
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      in0 = {{1'b1, 1'b0}, {1'b0, 1'b1}};
+      if (cyc == 9) begin
+         $display("%p %p", in0, out0);
+         $display("%p %p", in1, out1);
+         if (out0[0] != 2'h2 || out0[1] != 2'h1) $stop;
+         if (out1[0] != 2'h2 || out1[1] != 2'h1) $stop;
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule
+
+module Sub
+  (input bit [1:0] in,
+   output bit [1:0] out);
+   assign out = in;
+endmodule