From 7ea014dab53e9341ed2bda0a76d948d4029546ce Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 23 Mar 2021 19:49:57 -0400
Subject: [PATCH] Fix false WIDTHCONCAT on casted constant (#2849).

---
 Changes                 | 1 +
 src/V3Width.cpp         | 1 +
 test_regress/t/t_cast.v | 7 +++++++
 3 files changed, 9 insertions(+)

diff --git a/Changes b/Changes
index 6040d6b58..a69c14979 100644
--- a/Changes
+++ b/Changes
@@ -24,6 +24,7 @@ Verilator 4.201 devel
 * Fix --timescale-override not suppressing TIMESCALEMOD (#2838). [Kaleb Barrett]
 * Fix false TIMESCALEMOD on generate-ignored instances (#2838). [Kaleb Barrett]
 * Fix --output-split with class extends (#2839). [Iru Cai]
+* Fix false WIDTHCONCAT on casted constant (#2849). [Rupert Swarbrick]
 
 
 Verilator 4.200 2021-03-12
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index a8ad15b01..62e1a945f 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -1821,6 +1821,7 @@ private:
         if (m_vup->final()) {
             // CastSize not needed once sizes determined
             AstNode* underp = nodep->lhsp()->unlinkFrBack();
+            underp->dtypeFrom(nodep);
             nodep->replaceWith(underp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         }
diff --git a/test_regress/t/t_cast.v b/test_regress/t/t_cast.v
index b41caa110..3a6cfe81c 100644
--- a/test_regress/t/t_cast.v
+++ b/test_regress/t/t_cast.v
@@ -46,6 +46,10 @@ module t;
 				  (27'(coeff1 * samp1) >>> 11) +
 				  (27'(coeff2 * samp2) >>> 11)); // 15' size casting to avoid synthesis/simulator warnings
 
+   logic one = 1'b1;
+   logic [32:0] b33 = {32'(0), one};
+   logic [31:0] b32 = {31'(0), one};
+
    initial begin
       if (logic8bit != 8'h12) $stop;
       if (4'shf > 4'sh0) $stop;
@@ -79,6 +83,9 @@ module t;
       if (27'h7ffecec != mida) $stop;
       if (27'h7ffecec != midb) $stop;
 
+      if (b33 != 33'b1) $stop;
+      if (b32 != 32'b1) $stop;
+
       $write("*-* All Finished *-*\n");
       $finish;
    end