diff --git a/include/verilated.h b/include/verilated.h
index e1ccdb6e3..f9cb28fbe 100644
--- a/include/verilated.h
+++ b/include/verilated.h
@@ -1587,12 +1587,14 @@ static inline QData VL_DIVS_QQQ(int lbits, QData lhs, QData rhs) VL_PURE {
 }
 static inline IData VL_MODDIVS_III(int lbits, IData lhs, IData rhs) VL_PURE {
     if (VL_UNLIKELY(rhs == 0)) return 0;
+    if (VL_UNLIKELY(lhs == 0x80000000 && rhs == 0xffffffff)) return 0;
     vlsint32_t lhs_signed = VL_EXTENDS_II(VL_IDATASIZE, lbits, lhs);
     vlsint32_t rhs_signed = VL_EXTENDS_II(VL_IDATASIZE, lbits, rhs);
     return lhs_signed % rhs_signed;
 }
 static inline QData VL_MODDIVS_QQQ(int lbits, QData lhs, QData rhs) VL_PURE {
     if (VL_UNLIKELY(rhs == 0)) return 0;
+    if (VL_UNLIKELY(lhs == 0x8000000000000000ULL && rhs == 0xffffffffffffffffULL)) return 0;
     vlsint64_t lhs_signed = VL_EXTENDS_QQ(VL_QUADSIZE, lbits, lhs);
     vlsint64_t rhs_signed = VL_EXTENDS_QQ(VL_QUADSIZE, lbits, rhs);
     return lhs_signed % rhs_signed;
diff --git a/test_regress/t/t_math_div0.v b/test_regress/t/t_math_div0.v
index ad6bc069c..2612c5fb4 100644
--- a/test_regress/t/t_math_div0.v
+++ b/test_regress/t/t_math_div0.v
@@ -5,20 +5,24 @@
 
 module t(/*AUTOARG*/
    // Outputs
-   y, y2, y3
+   y, d2, m2, d3, m3
    );
    output [3:0] y;
-   output [31:0] y2;
-   output [63:0] y3;
+   output [31:0] d2;
+   output [31:0] m2;
+   output [63:0] d3;
+   output [63:0] m3;
    // bug775
    // verilator lint_off WIDTH
    assign y = ((0/0) ? 1 : 2) % 0;
 
    // bug2460
    reg [31:0]    b;
-   assign y2 = $signed(32'h80000000) / $signed(b);
+   assign d2 = $signed(32'h80000000) / $signed(b);
+   assign m2 = $signed(32'h80000000) % $signed(b);
    reg [63:0]    b3;
-   assign y3 = $signed(64'h80000000_00000000) / $signed(b3);
+   assign d3 = $signed(64'h80000000_00000000) / $signed(b3);
+   assign m3 = $signed(64'h80000000_00000000) % $signed(b3);
 
    initial begin
       b = 32'hffffffff;