Fix consecutive zero-delays (#5038)

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>

include/verilated_timing.cpp

@@ -67,9 +67,16 @@ void VlDelayScheduler::resume() {
     }
 
     if (!m_zeroDelayed.empty()) {
-        for (auto&& handle : m_zeroDelayed) handle.resume();
-        m_zeroDelayed.clear();
+        // First, we need to move the coroutines out of the queue, as a resumed coroutine can
+        // suspend on #0 again, adding itself to the queue, which can result in reallocating the
+        // queue mid-iteration.
+        // We swap with the m_zeroDlyResumed field to keep the allocated buffer.
+        m_zeroDlyResumed.swap(m_zeroDelayed);
+        for (auto&& handle : m_zeroDlyResumed) handle.resume();
+        m_zeroDlyResumed.clear();
         resumed = true;
+        // We are now in the Active region, so any coroutines added to m_zeroDelayed in the
+        // meantime will have to wait until the next Inactive region.
     }
 
     if (!resumed) {

include/verilated_timing.h

@@ -165,6 +165,9 @@ class VlDelayScheduler final {
     VerilatedContext& m_context;
     VlDelayedCoroutineQueue m_queue;  // Coroutines to be restored at a certain simulation time
     std::vector<VlCoroutineHandle> m_zeroDelayed;  // Coroutines waiting for #0
+    std::vector<VlCoroutineHandle> m_zeroDlyResumed;  // Coroutines that waited for #0 and are
+                                                      // to be resumed. Kept as a field to avoid
+                                                      // reallocation.
 
 public:
     // CONSTRUCTORS

test_regress/t/t_timing_zerodly_consecutive.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ["--exe --main --timing"],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_timing_zerodly_consecutive.v

@@ -0,0 +1,14 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+  initial begin
+    #0;
+    #0;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule