From 798bbe98e80009b57fd9472d648d64a82ca372a5 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 25 Sep 2024 22:40:28 -0400
Subject: [PATCH] Add syntax error on empty case items, per IEEE grammar.

---
 src/verilog.y                       | 33 +++++------------------------
 test_regress/t/t_case_wild.v        |  3 ---
 test_regress/t/t_pp_underline_bad.v |  1 +
 3 files changed, 6 insertions(+), 31 deletions(-)

diff --git a/src/verilog.y b/src/verilog.y
index ec95425b2..6c6589f4f 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -2903,7 +2903,7 @@ c_generate_item<nodep>:  // IEEE: generate_item (for checkers)
         ;
 
 conditional_generate_construct<nodep>:  // ==IEEE: conditional_generate_construct
-                yCASE '(' exprTypeCompare ')' ~c~case_generate_itemListE yENDCASE
+                yCASE '(' exprTypeCompare ')' ~c~case_generate_itemList yENDCASE
                         { $$ = new AstGenCase{$1, $3, $5}; }
         |       yIF '(' exprTypeCompare ')' ~c~generate_block_or_null %prec prLOWER_THAN_ELSE
                         { $$ = new AstGenIf{$1, $3, $5, nullptr}; }
@@ -2994,15 +2994,6 @@ genvar_iteration<nodep>:        // ==IEEE: genvar_iteration
                                                                 new AstConst{$2, AstConst::StringToParse{}, "'b1"}}}; }
         ;
 
-case_generate_itemListE<caseItemp>: // IEEE: [{ case_generate_itemList }]
-                /* empty */                             { $$ = nullptr; }
-        |       ~c~case_generate_itemList               { $$ = $1; }
-        ;
-
-c_case_generate_itemListE<caseItemp>:  // IEEE: { case_generate_item } (for checkers)
-                BISONPRE_COPY(case_generate_itemListE,{s/~c~/c_/g})      // {copied}
-        ;
-
 case_generate_itemList<caseItemp>:  // IEEE: { case_generate_itemList }
                 ~c~case_generate_item                   { $$ = $1; }
         |       ~c~case_generate_itemList ~c~case_generate_item         { $$ = $1; $1->addNext($2); }
@@ -3621,15 +3612,15 @@ statement_item<nodep>:          // IEEE: statement_item
                         { $$ = new AstRelease{$1, $2}; v3Global.setHasForceableSignals(); }
         //
         //                      // IEEE: case_statement
-        |       unique_priorityE caseStart caseAttrE case_itemListE yENDCASE
+        |       unique_priorityE caseStart caseAttrE case_itemList yENDCASE
                         { $$ = $2; if ($4) $2->addItemsp($4);
                           if ($1 == uniq_UNIQUE) $2->uniquePragma(true);
                           if ($1 == uniq_UNIQUE0) $2->unique0Pragma(true);
                           if ($1 == uniq_PRIORITY) $2->priorityPragma(true); }
-        // &&& is part of expr so case_patternListE aliases to case_itemListE
-        |       unique_priorityE caseStart caseAttrE yMATCHES case_patternListE yENDCASE
+        // &&& is part of expr so case_patternList aliases to case_itemList
+        |       unique_priorityE caseStart caseAttrE yMATCHES case_itemList yENDCASE
                         { $$ = nullptr; BBUNSUP($4, "Unsupported: matches (for tagged union)"); }
-        |       unique_priorityE caseStart caseAttrE yINSIDE case_insideListE yENDCASE
+        |       unique_priorityE caseStart caseAttrE yINSIDE case_inside_itemList yENDCASE
                         { $$ = $2; if ($5) $2->addItemsp($5);
                           if (!$2->caseSimple()) $4->v3error("Illegal to have inside on a casex/casez");
                           $2->caseInsideSet();
@@ -3887,20 +3878,6 @@ caseAttrE:
         |       caseAttrE yVL_PARALLEL_CASE             { GRAMMARP->m_caseAttrp->parallelPragma(true); }
         ;
 
-case_patternListE<caseItemp>:  // IEEE: case_pattern_item
-                case_itemListE                          { $$ = $1; }
-        ;
-
-case_itemListE<caseItemp>:      // IEEE: [ { case_item } ]
-                /* empty */                             { $$ = nullptr; }
-        |       case_itemList                           { $$ = $1; }
-        ;
-
-case_insideListE<caseItemp>:    // IEEE: [ { case_inside_item } ]
-                /* empty */                             { $$ = nullptr; }
-        |       case_inside_itemList                    { $$ = $1; }
-        ;
-
 case_itemList<caseItemp>:       // IEEE: { case_item + ... }
                 caseCondList colon stmtBlock                    { $$ = new AstCaseItem{$2, $1, $3}; }
         |       yDEFAULT colon stmtBlock                        { $$ = new AstCaseItem{$1, nullptr, $3}; }
diff --git a/test_regress/t/t_case_wild.v b/test_regress/t/t_case_wild.v
index ac8db4014..ef2002a14 100644
--- a/test_regress/t/t_case_wild.v
+++ b/test_regress/t/t_case_wild.v
@@ -60,9 +60,6 @@ module sub (/*AUTOARG*/
    output reg [4:0]  out2;
 
    always @* begin
-      // Test empty cases
-      casez (in[0])
-      endcase
       casez (in)
         24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00};
         24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00};
diff --git a/test_regress/t/t_pp_underline_bad.v b/test_regress/t/t_pp_underline_bad.v
index adcd87d58..7d1ee1bc9 100644
--- a/test_regress/t/t_pp_underline_bad.v
+++ b/test_regress/t/t_pp_underline_bad.v
@@ -8,6 +8,7 @@ module t;
    // verilator_no_inline_module
    initial begin
       case (1'b1) // synopsys_full_case
+        1'b0: $stop;
       endcase
       $stop; // Should have failed
    end