Fix coverage counts missing due to table optimization (#5473) (#5474).

Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org>
This commit is contained in:
Vito Gamberini 2024-10-10 21:22:06 -04:00 committed by Wilson Snyder
parent 3cced9baad
commit 789698cb5c
8 changed files with 503 additions and 304 deletions

11
Changes
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@ -28,7 +28,7 @@ Verilator 5.029 devel
* Support packed/unpacked and dynamic array unconstrained randomization (#5414) (#5415). [Yilou Wang]
* Support appending to queue via `[]` (#5421). [Krzysztof Bieganski, Antmicro Ltd.]
* Support named event locals (#5422). [Krzysztof Bieganski, Antmicro Ltd.]
* Support basic dist constraints (#5431). [Arkadiusz Kozdra, Antmicro Ltd.]
* Support basic `dist` constraints (#5431). [Arkadiusz Kozdra, Antmicro Ltd.]
* Support unpacked array constrained randomization (#5437) (#5489). [Yilou Wang]
* Support inside array constraints (#5448). [Arkadiusz Kozdra, Antmicro Ltd.]
* Support DPI imports and exports with double underscores (#5481).
@ -61,19 +61,20 @@ Verilator 5.029 devel
* Fix queue `[$-i]` select as reference argument (#5411). [Krzysztof Bieganski, Antmicro Ltd.]
* Fix `pre`/`post_randomize` on `randomize() with` (#5412). [Krzysztof Bieganski, Antmicro Ltd.]
* Fix capturing params in `randomize() with` (#5416) (#5418). [Krzysztof Bieganski, Antmicro Ltd.]
* Fix sformatf internal error on initial automatics (#5423). [Todd Strader]
* Fix `sformatf` internal error on initial automatics (#5423). [Todd Strader]
* Fix clearing trigger of events with no sensitivity trees (#5426). [Arkadiusz Kozdra, Antmicro Ltd.]
* Fix driving clocking block in reactive region (#5430). [Krzysztof Bieganski, Antmicro Ltd.]
* Fix associative array next/prev/first/last mis-propagating constants (#5435). [Ethan Sifferman]
* Fix randomize treated as std::randomize in classes (#5436). [Arkadiusz Kozdra, Antmicro Ltd.]
* Fix foreach colliding index names (#5444). [Arkadiusz Kozdra, Antmicro Ltd.]
* Fix `foreach` colliding index names (#5444). [Arkadiusz Kozdra, Antmicro Ltd.]
* Fix fault on defparam with UNSUPPORTED ignored (#5450). [Luiza de Melo]
* Fix class reference with pin that is a class reference (#5454).
* Fix not reporting class reference with extra parameters (#5467).
* Fix user-type parameter overlap (#5469). [Todd Strader]
* Fix tracing when name() is empty (#5470). [Sam Shahrestani]
* Fix timing mode not exiting on empty events (#5472).
* Fix --binary with .cpp PLI filenames under relative directory paths.
* Fix coverage counts missing due to table optimization (#5473) (#5474). [Vito Gamberini]
* Fix `--binary` with .cpp PLI filenames under relative directory paths.
* Fix extra dot in coverage point hierarchy when using name()=''.
* Fix short-circuiting with associative array access (#5484). [Ethan Sifferman]
* Fix short-circuiting on method calls (#5486). [Ethan Sifferman]
@ -83,7 +84,7 @@ Verilator 5.029 devel
* Fix explicit CMAKE_INSTALL_PREFIX usages (#5500). [Fabian Keßler]
* Fix configure inserting absolute paths for Python and Perl (#5504) (#5505). [Nathan Graybeal]
* Fix pattern initialization with typedef key (#5512). [Eugene Feinberg]
* Fix -j option without argument in hierarchical Verilation (#5514). [Ryszard Rozak, Antmicro Ltd.]
* Fix `-j` option without argument in hierarchical Verilation (#5514). [Ryszard Rozak, Antmicro Ltd.]
Verilator 5.028 2024-08-21

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@ -108,6 +108,7 @@ private:
bool m_anyAssignComb; ///< True if found a non-delayed assignment
bool m_inDlyAssign; ///< Under delayed assignment
bool m_isImpure; // Not pure
bool m_isCoverage; // Has coverage
int m_instrCount; ///< Number of nodes
int m_dataCount; ///< Bytes of data
AstJumpGo* m_jumpp = nullptr; ///< Jump label we're branching from
@ -215,6 +216,7 @@ public:
bool isAssignDly() const { return m_anyAssignDly; }
bool isImpure() const { return m_isImpure; }
bool isCoverage() const { return m_isCoverage; }
int instrCount() const { return m_instrCount; }
int dataCount() const { return m_dataCount; }
@ -1196,8 +1198,7 @@ private:
}
}
// Ignore coverage - from a function we're inlining
void visit(AstCoverInc* nodep) override {}
void visit(AstCoverInc* nodep) override { m_isCoverage = true; }
// ====
// Known Bad
@ -1248,6 +1249,7 @@ public:
m_anyAssignDly = false;
m_inDlyAssign = false;
m_isImpure = false;
m_isCoverage = false;
m_instrCount = 0;
m_dataCount = 0;
m_jumpp = nullptr;

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@ -210,6 +210,9 @@ private:
const double time // max(_, 1), so we won't divide by zero
= std::max<double>(chkvis.instrCount() * TABLE_BYTES_PER_INST + chkvis.dataCount(), 1);
if (chkvis.isImpure()) chkvis.clearOptimizable(nodep, "Table creates side effects");
if (chkvis.isCoverage()) {
chkvis.clearOptimizable(nodep, "Table removes coverage points");
}
if (!m_outWidthBytes || !m_inWidthBits) {
chkvis.clearOptimizable(nodep, "Table has no outputs");
}

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@ -46,6 +46,10 @@
// Inputs
.clk (clk),
.toggle (toggle));
tab tab1 (/*AUTOINST*/
// Inputs
.clk (clk));
par par1 (/*AUTOINST*/);
000010 always @ (posedge clk) begin
+000010 point: comment=block
@ -139,11 +143,11 @@
%000000 do ; while (0);
-000000 point: comment=block
~000010 do begin
+000010 point: comment=if
-000000 point: comment=block
+000010 point: comment=if
~000010 $write("");
+000010 point: comment=if
-000000 point: comment=block
+000010 point: comment=if
%000000 end while (0);
-000000 point: comment=block
//===
@ -190,14 +194,14 @@
input toggle;
000020 always @ (posedge clk) begin
+000020 point: comment=block
~000018 if (toggle) begin // CHECK_COVER(0,"top.t.a*",2)
~000018 if (toggle) begin // CHECK_COVER(0,"top.t.a*",18)
-000002 point: comment=if
+000018 point: comment=else
%000002 $write("");
-000002 point: comment=if
// t.a1 and t.a2 collapse to a count of 2
end
000018 if (toggle) begin
000018 if (toggle) begin // *** t_cover_line.vlt turns this off
+000018 point: comment=else
$write(""); // CHECK_COVER_MISSING(0)
// This doesn't even get added
@ -241,7 +245,7 @@
`ifdef ATTRIBUTE
// verilator coverage_block_off
`endif
begin end // Needed for .vlt to attach coverage_block_off
begin end // *** t_cover_line.vlt turns this off (so need begin/end)
if (1) begin end // CHECK_COVER_MISSING(0)
$write(""); // CHECK_COVER_MISSING(0)
end
@ -272,7 +276,7 @@
endfunction
000011 function void fauto();
+000011 point: comment=block
~000011 if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",1)
~000011 if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",11)
+000011 point: comment=if
-000000 point: comment=else
000011 $write("");
@ -324,7 +328,6 @@
+000011 point: comment=block
end
endtask
endmodule
module off (/*AUTOARG*/
@ -355,6 +358,60 @@
-000001 point: comment=else
end
end
endmodule
module tab (input clk);
bit [3:0] cyc4;
int decoded;
000010 always @ (posedge clk) begin
+000010 point: comment=block
000010 case (cyc4)
+000010 point: comment=block
%000001 1: decoded = 10;
-000001 point: comment=case
%000001 2: decoded = 20;
-000001 point: comment=case
%000001 3: decoded = 30;
-000001 point: comment=case
%000001 4: decoded = 40;
-000001 point: comment=case
%000001 5: decoded = 50;
-000001 point: comment=case
%000005 default: decoded = 0;
-000005 point: comment=case
endcase
end
000010 always @ (posedge clk) begin
+000010 point: comment=block
000010 cyc4 <= cyc4 + 1;
+000010 point: comment=block
end
endmodule
module par();
localparam int CALLS_FUNC = param_func(1);
// We don't currently count elaboration time use towards coverage. This
// seems safer for functions used both at elaboration time and not - but may
// revisit this.
%000000 function automatic int param_func(int i);
-000000 point: comment=block
%000000 if (i == 0) begin
-000000 point: comment=if
-000000 point: comment=else
%000000 i = 99; // Uncovered
-000000 point: comment=if
end
%000000 else begin
-000000 point: comment=else
%000000 i = i + 1;
-000000 point: comment=else
end
%000000 return i;
-000000 point: comment=block
endfunction
endmodule

View File

@ -43,6 +43,10 @@ module t (/*AUTOARG*/
// Inputs
.clk (clk),
.toggle (toggle));
tab tab1 (/*AUTOINST*/
// Inputs
.clk (clk));
par par1 (/*AUTOINST*/);
always @ (posedge clk) begin
if (cyc!=0) begin
@ -130,11 +134,11 @@ module alpha (/*AUTOARG*/
input clk;
input toggle;
always @ (posedge clk) begin
if (toggle) begin // CHECK_COVER(0,"top.t.a*",2)
if (toggle) begin // CHECK_COVER(0,"top.t.a*",18)
$write("");
// t.a1 and t.a2 collapse to a count of 2
end
if (toggle) begin
if (toggle) begin // *** t_cover_line.vlt turns this off
$write(""); // CHECK_COVER_MISSING(0)
// This doesn't even get added
`ifdef ATTRIBUTE
@ -168,7 +172,7 @@ module beta (/*AUTOARG*/
`ifdef ATTRIBUTE
// verilator coverage_block_off
`endif
begin end // Needed for .vlt to attach coverage_block_off
begin end // *** t_cover_line.vlt turns this off (so need begin/end)
if (1) begin end // CHECK_COVER_MISSING(0)
$write(""); // CHECK_COVER_MISSING(0)
end
@ -189,7 +193,7 @@ class Cls;
end
endfunction
function void fauto();
if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",1)
if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",11)
$write("");
end
endfunction
@ -224,7 +228,6 @@ module tsk (/*AUTOARG*/
Cls::fstatic(1'b1);
end
endtask
endmodule
module off (/*AUTOARG*/
@ -249,5 +252,42 @@ module off (/*AUTOARG*/
if (0) ; // CHECK_COVER(0,"top.t.o1",1)
end
end
endmodule
module tab (input clk);
bit [3:0] cyc4;
int decoded;
always @ (posedge clk) begin
case (cyc4)
1: decoded = 10;
2: decoded = 20;
3: decoded = 30;
4: decoded = 40;
5: decoded = 50;
default: decoded = 0;
endcase
end
always @ (posedge clk) begin
cyc4 <= cyc4 + 1;
end
endmodule
module par();
localparam int CALLS_FUNC = param_func(1);
// We don't currently count elaboration time use towards coverage. This
// seems safer for functions used both at elaboration time and not - but may
// revisit this.
function automatic int param_func(int i);
if (i == 0) begin
i = 99; // Uncovered
end
else begin
i = i + 1;
end
return i;
endfunction
endmodule

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@ -6,6 +6,6 @@
`verilator_config
coverage_block_off -file "t/t_cover_line.v" -lines 137
coverage_block_off -file "t/t_cover_line.v" -lines 171
coverage_block_off -file "t/t_cover_line.v" -lines 141
coverage_block_off -file "t/t_cover_line.v" -lines 175
coverage_block_off -module "beta" -block "block"

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@ -2,130 +2,148 @@ TN:verilator_coverage
SF:t/t_cover_line.v
DA:15,1
DA:18,1
DA:47,10
DA:48,10
BRDA:48,0,0,10
BRDA:48,0,1,0
DA:49,10
DA:50,10
DA:52,9
BRDA:52,0,0,1
BRDA:52,0,1,9
DA:53,9
BRDA:53,0,0,1
BRDA:53,0,1,9
DA:54,1
DA:55,1
DA:58,9
BRDA:58,0,0,1
BRDA:58,0,1,9
DA:59,9
BRDA:59,0,0,1
BRDA:59,0,1,9
DA:61,9
DA:51,10
DA:52,10
BRDA:52,0,0,10
BRDA:52,0,1,0
DA:53,10
DA:54,10
DA:56,9
BRDA:56,0,0,1
BRDA:56,0,1,9
DA:57,9
BRDA:57,0,0,1
BRDA:57,0,1,9
DA:58,1
DA:59,1
DA:62,9
BRDA:62,0,0,1
BRDA:62,0,1,9
DA:63,9
BRDA:63,0,0,1
BRDA:63,0,1,9
DA:65,9
BRDA:65,0,0,1
BRDA:65,0,1,9
DA:66,9
BRDA:66,0,0,1
BRDA:66,0,1,9
DA:67,1
DA:68,1
DA:71,9
DA:72,9
DA:75,1
DA:76,1
DA:77,1
DA:69,9
BRDA:69,0,0,1
BRDA:69,0,1,9
DA:70,9
BRDA:70,0,0,1
BRDA:70,0,1,9
DA:71,1
DA:72,1
DA:75,9
DA:76,9
DA:79,1
DA:80,1
DA:81,1
DA:83,7
BRDA:83,0,0,1
BRDA:83,0,1,7
DA:83,1
DA:84,1
DA:85,1
DA:88,7
DA:89,7
DA:92,0
DA:93,0
DA:94,0
DA:87,7
BRDA:87,0,0,1
BRDA:87,0,1,7
DA:88,1
DA:89,1
DA:92,7
DA:93,7
DA:96,0
DA:97,10
BRDA:97,0,0,10
BRDA:97,0,1,0
DA:98,10
BRDA:98,0,0,10
BRDA:98,0,1,0
DA:99,0
DA:102,1
DA:103,1
DA:105,1
DA:97,0
DA:98,0
DA:100,0
DA:101,10
BRDA:101,0,0,0
BRDA:101,0,1,10
DA:102,10
BRDA:102,0,0,0
BRDA:102,0,1,10
DA:103,0
DA:106,1
DA:107,1
DA:112,7
BRDA:112,0,0,1
BRDA:112,0,1,7
DA:113,1
DA:114,1
DA:119,1
DA:121,1
DA:132,20
DA:133,18
BRDA:133,0,0,2
BRDA:133,0,1,18
DA:134,2
DA:109,1
DA:111,1
DA:116,7
BRDA:116,0,0,1
BRDA:116,0,1,7
DA:117,1
DA:118,1
DA:123,1
DA:125,1
DA:136,20
DA:137,18
DA:156,20
DA:157,20
DA:158,20
BRDA:158,0,0,0
BRDA:158,0,1,20
DA:160,0
DA:162,18
BRDA:162,0,0,2
BRDA:162,0,1,18
DA:164,2
BRDA:137,0,0,2
BRDA:137,0,1,18
DA:138,2
DA:141,18
DA:160,20
DA:161,20
DA:162,20
BRDA:162,0,0,0
BRDA:162,0,1,20
DA:164,0
DA:166,18
DA:180,1
DA:181,1
DA:182,1
BRDA:182,0,0,1
BRDA:182,0,1,0
DA:183,1
DA:186,11
DA:187,11
BRDA:187,0,0,11
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DA:188,11
BRDA:166,0,0,2
BRDA:166,0,1,18
DA:168,2
DA:170,18
DA:184,1
DA:185,1
DA:186,1
BRDA:186,0,0,1
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DA:187,1
DA:190,11
DA:191,11
BRDA:191,0,0,11
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DA:192,11
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DA:193,11
DA:207,10
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DA:215,1
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DA:218,1
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BRF:44
BRH:10
end_of_record

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@ -1,100 +1,118 @@
$version Generated by VerilatedVcd $end
$timescale 1ps $end
$scope module top $end
$scope module t $end
$var wire 1 X clk $end
$var wire 1 b clk $end
$var wire 1 & toggle $end
$var wire 32 # vlCoverageLineTrace_t_cover_line__15_block [31:0] $end
$var wire 32 ' cyc [31:0] $end
$var wire 32 $ vlCoverageLineTrace_t_cover_line__18_block [31:0] $end
$var wire 8 ( cyc_copy [7:0] $end
$scope module b1 $end
$var wire 1 X clk $end
$var wire 1 b clk $end
$var wire 1 & toggle $end
$var wire 32 L vlCoverageLineTrace_t_cover_line__156_block [31:0] $end
$var wire 32 M vlCoverageLineTrace_t_cover_line__158_else [31:0] $end
$var wire 32 c vlCoverageLineTrace_t_cover_line__158_if [31:0] $end
$var wire 32 N vlCoverageLineTrace_t_cover_line__162_else [31:0] $end
$var wire 32 O vlCoverageLineTrace_t_cover_line__162_if [31:0] $end
$var wire 32 P vlCoverageLineTrace_t_cover_line__166_else [31:0] $end
$var wire 32 V vlCoverageLineTrace_t_cover_line__160_block [31:0] $end
$var wire 32 W vlCoverageLineTrace_t_cover_line__162_else [31:0] $end
$var wire 32 q vlCoverageLineTrace_t_cover_line__162_if [31:0] $end
$var wire 32 X vlCoverageLineTrace_t_cover_line__166_else [31:0] $end
$var wire 32 Y vlCoverageLineTrace_t_cover_line__166_if [31:0] $end
$var wire 32 Z vlCoverageLineTrace_t_cover_line__170_else [31:0] $end
$upscope $end
$scope module b2 $end
$var wire 1 X clk $end
$var wire 1 b clk $end
$var wire 1 & toggle $end
$var wire 32 Q vlCoverageLineTrace_t_cover_line__156_block [31:0] $end
$var wire 32 R vlCoverageLineTrace_t_cover_line__158_else [31:0] $end
$var wire 32 d vlCoverageLineTrace_t_cover_line__158_if [31:0] $end
$var wire 32 S vlCoverageLineTrace_t_cover_line__162_else [31:0] $end
$var wire 32 T vlCoverageLineTrace_t_cover_line__162_if [31:0] $end
$var wire 32 U vlCoverageLineTrace_t_cover_line__166_else [31:0] $end
$var wire 32 [ vlCoverageLineTrace_t_cover_line__160_block [31:0] $end
$var wire 32 \ vlCoverageLineTrace_t_cover_line__162_else [31:0] $end
$var wire 32 r vlCoverageLineTrace_t_cover_line__162_if [31:0] $end
$var wire 32 ] vlCoverageLineTrace_t_cover_line__166_else [31:0] $end
$var wire 32 ^ vlCoverageLineTrace_t_cover_line__166_if [31:0] $end
$var wire 32 _ vlCoverageLineTrace_t_cover_line__170_else [31:0] $end
$upscope $end
$scope module t1 $end
$var wire 1 X clk $end
$var wire 1 b clk $end
$var wire 1 & toggle $end
$var wire 32 V vlCoverageLineTrace_t_cover_line__207_block [31:0] $end
$var wire 32 Z vlCoverageLineTrace_t_cover_line__211_block [31:0] $end
$var wire 32 [ vlCoverageLineTrace_t_cover_line__214_else [31:0] $end
$var wire 32 \ vlCoverageLineTrace_t_cover_line__214_if [31:0] $end
$var wire 32 W vlCoverageLineTrace_t_cover_line__217_else [31:0] $end
$var wire 32 ] vlCoverageLineTrace_t_cover_line__217_if [31:0] $end
$var wire 32 % vlCoverageLineTrace_t_cover_line__222_block [31:0] $end
$var wire 32 ` vlCoverageLineTrace_t_cover_line__211_block [31:0] $end
$var wire 32 d vlCoverageLineTrace_t_cover_line__215_block [31:0] $end
$var wire 32 e vlCoverageLineTrace_t_cover_line__218_else [31:0] $end
$var wire 32 f vlCoverageLineTrace_t_cover_line__218_if [31:0] $end
$var wire 32 a vlCoverageLineTrace_t_cover_line__221_else [31:0] $end
$var wire 32 g vlCoverageLineTrace_t_cover_line__221_if [31:0] $end
$var wire 32 % vlCoverageLineTrace_t_cover_line__226_block [31:0] $end
$upscope $end
$var wire 32 ) vlCoverageLineTrace_t_cover_line__47_block [31:0] $end
$var wire 32 * vlCoverageLineTrace_t_cover_line__48_else [31:0] $end
$var wire 32 + vlCoverageLineTrace_t_cover_line__48_if [31:0] $end
$var wire 32 , vlCoverageLineTrace_t_cover_line__52_else [31:0] $end
$var wire 32 - vlCoverageLineTrace_t_cover_line__52_if [31:0] $end
$var wire 32 . vlCoverageLineTrace_t_cover_line__53_else [31:0] $end
$var wire 32 / vlCoverageLineTrace_t_cover_line__53_if [31:0] $end
$var wire 32 0 vlCoverageLineTrace_t_cover_line__58_else [31:0] $end
$var wire 32 1 vlCoverageLineTrace_t_cover_line__58_if [31:0] $end
$var wire 32 2 vlCoverageLineTrace_t_cover_line__59_else [31:0] $end
$var wire 32 3 vlCoverageLineTrace_t_cover_line__59_if [31:0] $end
$var wire 32 4 vlCoverageLineTrace_t_cover_line__65_else [31:0] $end
$var wire 32 5 vlCoverageLineTrace_t_cover_line__65_if [31:0] $end
$var wire 32 6 vlCoverageLineTrace_t_cover_line__66_else [31:0] $end
$var wire 32 7 vlCoverageLineTrace_t_cover_line__66_if [31:0] $end
$var wire 32 8 vlCoverageLineTrace_t_cover_line__75_elsif [31:0] $end
$var wire 32 9 vlCoverageLineTrace_t_cover_line__79_elsif [31:0] $end
$var wire 32 : vlCoverageLineTrace_t_cover_line__83_else [31:0] $end
$var wire 32 ; vlCoverageLineTrace_t_cover_line__83_if [31:0] $end
$var wire 32 ^ vlCoverageLineTrace_t_cover_line__92_block [31:0] $end
$var wire 32 _ vlCoverageLineTrace_t_cover_line__93_block [31:0] $end
$var wire 32 ` vlCoverageLineTrace_t_cover_line__96_block [31:0] $end
$var wire 32 a vlCoverageLineTrace_t_cover_line__97_block [31:0] $end
$var wire 32 < vlCoverageLineTrace_t_cover_line__102_elsif [31:0] $end
$var wire 32 = vlCoverageLineTrace_t_cover_line__105_elsif [31:0] $end
$var wire 32 > vlCoverageLineTrace_t_cover_line__112_else [31:0] $end
$var wire 32 ? vlCoverageLineTrace_t_cover_line__112_if [31:0] $end
$var wire 32 Y vlCoverageLineTrace_t_cover_line__119_block [31:0] $end
$var wire 32 ) vlCoverageLineTrace_t_cover_line__51_block [31:0] $end
$var wire 32 * vlCoverageLineTrace_t_cover_line__52_else [31:0] $end
$var wire 32 + vlCoverageLineTrace_t_cover_line__52_if [31:0] $end
$var wire 32 , vlCoverageLineTrace_t_cover_line__56_else [31:0] $end
$var wire 32 - vlCoverageLineTrace_t_cover_line__56_if [31:0] $end
$var wire 32 . vlCoverageLineTrace_t_cover_line__57_else [31:0] $end
$var wire 32 / vlCoverageLineTrace_t_cover_line__57_if [31:0] $end
$var wire 32 0 vlCoverageLineTrace_t_cover_line__62_else [31:0] $end
$var wire 32 1 vlCoverageLineTrace_t_cover_line__62_if [31:0] $end
$var wire 32 2 vlCoverageLineTrace_t_cover_line__63_else [31:0] $end
$var wire 32 3 vlCoverageLineTrace_t_cover_line__63_if [31:0] $end
$var wire 32 4 vlCoverageLineTrace_t_cover_line__69_else [31:0] $end
$var wire 32 5 vlCoverageLineTrace_t_cover_line__69_if [31:0] $end
$var wire 32 6 vlCoverageLineTrace_t_cover_line__70_else [31:0] $end
$var wire 32 7 vlCoverageLineTrace_t_cover_line__70_if [31:0] $end
$var wire 32 8 vlCoverageLineTrace_t_cover_line__79_elsif [31:0] $end
$var wire 32 9 vlCoverageLineTrace_t_cover_line__83_elsif [31:0] $end
$var wire 32 : vlCoverageLineTrace_t_cover_line__87_else [31:0] $end
$var wire 32 ; vlCoverageLineTrace_t_cover_line__87_if [31:0] $end
$var wire 32 h vlCoverageLineTrace_t_cover_line__96_block [31:0] $end
$var wire 32 i vlCoverageLineTrace_t_cover_line__97_block [31:0] $end
$var wire 32 j vlCoverageLineTrace_t_cover_line__100_block [31:0] $end
$var wire 32 k vlCoverageLineTrace_t_cover_line__101_block [31:0] $end
$var wire 32 < vlCoverageLineTrace_t_cover_line__106_elsif [31:0] $end
$var wire 32 = vlCoverageLineTrace_t_cover_line__109_elsif [31:0] $end
$var wire 32 > vlCoverageLineTrace_t_cover_line__116_else [31:0] $end
$var wire 32 ? vlCoverageLineTrace_t_cover_line__116_if [31:0] $end
$var wire 32 c vlCoverageLineTrace_t_cover_line__123_block [31:0] $end
$scope module a1 $end
$var wire 1 X clk $end
$var wire 1 b clk $end
$var wire 1 & toggle $end
$var wire 32 @ vlCoverageLineTrace_t_cover_line__132_block [31:0] $end
$var wire 32 A vlCoverageLineTrace_t_cover_line__133_else [31:0] $end
$var wire 32 B vlCoverageLineTrace_t_cover_line__133_if [31:0] $end
$var wire 32 C vlCoverageLineTrace_t_cover_line__137_else [31:0] $end
$var wire 32 @ vlCoverageLineTrace_t_cover_line__136_block [31:0] $end
$var wire 32 A vlCoverageLineTrace_t_cover_line__137_else [31:0] $end
$var wire 32 B vlCoverageLineTrace_t_cover_line__137_if [31:0] $end
$var wire 32 C vlCoverageLineTrace_t_cover_line__141_else [31:0] $end
$upscope $end
$scope module a2 $end
$var wire 1 X clk $end
$var wire 1 b clk $end
$var wire 1 & toggle $end
$var wire 32 D vlCoverageLineTrace_t_cover_line__132_block [31:0] $end
$var wire 32 E vlCoverageLineTrace_t_cover_line__133_else [31:0] $end
$var wire 32 F vlCoverageLineTrace_t_cover_line__133_if [31:0] $end
$var wire 32 G vlCoverageLineTrace_t_cover_line__137_else [31:0] $end
$var wire 32 D vlCoverageLineTrace_t_cover_line__136_block [31:0] $end
$var wire 32 E vlCoverageLineTrace_t_cover_line__137_else [31:0] $end
$var wire 32 F vlCoverageLineTrace_t_cover_line__137_if [31:0] $end
$var wire 32 G vlCoverageLineTrace_t_cover_line__141_else [31:0] $end
$upscope $end
$scope module o1 $end
$var wire 1 X clk $end
$var wire 1 b clk $end
$var wire 1 & toggle $end
$var wire 32 H vlCoverageLineTrace_t_cover_line__245_block [31:0] $end
$var wire 32 I vlCoverageLineTrace_t_cover_line__246_else [31:0] $end
$var wire 32 J vlCoverageLineTrace_t_cover_line__246_if [31:0] $end
$var wire 32 K vlCoverageLineTrace_t_cover_line__249_else [31:0] $end
$var wire 32 b vlCoverageLineTrace_t_cover_line__249_if [31:0] $end
$var wire 32 H vlCoverageLineTrace_t_cover_line__248_block [31:0] $end
$var wire 32 I vlCoverageLineTrace_t_cover_line__249_else [31:0] $end
$var wire 32 J vlCoverageLineTrace_t_cover_line__249_if [31:0] $end
$var wire 32 K vlCoverageLineTrace_t_cover_line__252_else [31:0] $end
$var wire 32 l vlCoverageLineTrace_t_cover_line__252_if [31:0] $end
$upscope $end
$scope module par1 $end
$var wire 32 m CALLS_FUNC [31:0] $end
$var wire 32 n vlCoverageLineTrace_t_cover_line__283_block [31:0] $end
$var wire 32 o vlCoverageLineTrace_t_cover_line__284_else [31:0] $end
$var wire 32 p vlCoverageLineTrace_t_cover_line__284_if [31:0] $end
$upscope $end
$scope module tab1 $end
$var wire 1 b clk $end
$var wire 4 L cyc4 [3:0] $end
$var wire 32 M decoded [31:0] $end
$var wire 32 N vlCoverageLineTrace_t_cover_line__261_block [31:0] $end
$var wire 32 O vlCoverageLineTrace_t_cover_line__263_case [31:0] $end
$var wire 32 P vlCoverageLineTrace_t_cover_line__264_case [31:0] $end
$var wire 32 Q vlCoverageLineTrace_t_cover_line__265_case [31:0] $end
$var wire 32 R vlCoverageLineTrace_t_cover_line__266_case [31:0] $end
$var wire 32 S vlCoverageLineTrace_t_cover_line__267_case [31:0] $end
$var wire 32 T vlCoverageLineTrace_t_cover_line__268_case [31:0] $end
$var wire 32 U vlCoverageLineTrace_t_cover_line__272_block [31:0] $end
$upscope $end
$upscope $end
$var wire 1 X clk $end
$var wire 1 b clk $end
$upscope $end
$enddefinitions $end
@ -141,7 +159,7 @@ b00000000000000000000000000000000 H
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b00000000000000000000000000000010 '
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#15
0X
0b
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b00000000000000000000000000000011 '
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1&
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0X
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0&
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b00000000000000000000000000000110 '
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0X
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b00000000000000000000000000000111 '
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0X
0b
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0X
0b
#90
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0X
0b
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