github/verilator
1
0
Fork 1
mirror of https://github.com/verilator/verilator.git synced 2025-01-06 06:37:45 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fix DPI-C and protect-lib if port is implicit logic (#2699)

Browse Source
This commit is contained in:
Yutetsu TAKATSUKASA 2020-12-15 23:51:14 +09:00 committed by GitHub
parent 5ee30e271e
commit 7821da6ad5
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 23 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/V3Width.cpp
View File

@ -1446,6 +1446,20 @@ private:
// DTYPES
virtual void visit(AstNodeArrayDType* nodep) override {
if (nodep->didWidthAndSet()) return; // This node is a dtype & not both PRELIMed+FINALed
if (nodep->subDTypep() == nodep->basicp()) { // Innermost dimension
AstBasicDType* basicp = nodep->basicp();
// If basic dtype is LOGIC_IMPLICIT, it is actually 1 bit LOGIC
if (basicp->implicit()) {
UASSERT_OBJ(basicp->width() <= 1, basicp,
"must be 1 bit but actually " << basicp->width() << " bits");
AstBasicDType* newp = new AstBasicDType(
basicp->fileline(), AstBasicDTypeKwd::LOGIC, basicp->numeric());
newp->widthForce(1, 1);
basicp->replaceWith(newp);
VL_DO_DANGLING(pushDeletep(basicp), basicp);
}
}
// Iterate into subDTypep() to resolve that type and update pointer.
nodep->refDTypep(iterateEditMoveDTypep(nodep, nodep->subDTypep()));
// Cleanup array size

6
test_regress/t/t_prot_lib.v
View File

@ -41,6 +41,8 @@ module t #(parameter GATED_CLK = 0) (/*AUTOARG*/
logic [31:0] accum_bypass_out_expect;
logic s1_in;
logic s1_out;
logic s1up_in[2];
logic s1up_out[2];
logic [1:0] s2_in;
logic [1:0] s2_out;
logic [7:0] s8_in;
@ -74,6 +76,8 @@ module t #(parameter GATED_CLK = 0) (/*AUTOARG*/
.accum_bypass_out,
.s1_in,
.s1_out,
.s1up_in,
.s1up_out,
.s2_in,
.s2_out,
.s8_in,
@ -113,6 +117,7 @@ module t #(parameter GATED_CLK = 0) (/*AUTOARG*/
`DRIVE(s65)
`DRIVE(s129)
`DRIVE(s4x32)
{s1up_in[1], s1up_in[0]} <= {^crc, ~(^crc)};
{s6x16up_in[0][0], s6x16up_in[0][1], s6x16up_in[0][2]} <= crc[47:0];
{s6x16up_in[1][0], s6x16up_in[1][1], s6x16up_in[1][2]} <= ~crc[63:16];
{s8x16up_in[0][0], s8x16up_in[0][1], s8x16up_in[0][2], s8x16up_in[0][3]} <= crc;
@ -170,6 +175,7 @@ module t #(parameter GATED_CLK = 0) (/*AUTOARG*/
#1;
/* verilator lint_on STMTDLY */
`CHECK(s1)
`CHECK(s1up)
`CHECK(s2)
`CHECK(s8)
`CHECK(s33)

3
test_regress/t/t_prot_lib_secret.v
View File

@ -11,6 +11,8 @@ module secret #(parameter GATED_CLK = 0)
output [31:0] accum_bypass_out,
input s1_in,
output logic s1_out,
input s1up_in[2],
output logic s1up_out[2],
input [1:0] s2_in,
output logic [1:0] s2_out,
input [7:0] s8_in,
@ -61,6 +63,7 @@ module secret #(parameter GATED_CLK = 0)
// Test combinatorial paths of different sizes
always @(*) begin
s1_out = s1_in;
s1up_out = s1up_in;
s2_out = s2_in;
s8_out = s8_in;
s64_out = s64_in;