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Fix complex user type problem with --x-assign (#5543)
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@ -1333,9 +1333,10 @@ class LinkDotFindVisitor final : public VNVisitor {
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} else {
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findvarp->combineType(nodep);
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findvarp->fileline()->modifyStateInherit(nodep->fileline());
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if (nodep->getChildDTypep()->numeric().isSigned()
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&& !findvarp->getChildDTypep()->numeric().isSigned()) {
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findvarp->getChildDTypep()->numeric(VSigning{true});
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UASSERT_OBJ(nodep->subDTypep(), nodep, "Var has no type");
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if (nodep->subDTypep()->numeric().isSigned()
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&& !findvarp->subDTypep()->numeric().isSigned()) {
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findvarp->subDTypep()->numeric(VSigning{true});
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}
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AstBasicDType* const bdtypep
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= VN_CAST(findvarp->childDTypep(), BasicDType);
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@ -48,6 +48,7 @@ class UnknownVisitor final : public VNVisitor {
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// AstNode::user2p() -> AstIf* Inserted if assignment for conditional
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const VNUser1InUse m_inuser1;
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const VNUser2InUse m_inuser2;
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static const std::string m_xrandPrefix;
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// STATE
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AstNodeModule* m_modp = nullptr; // Current module
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@ -58,7 +59,7 @@ class UnknownVisitor final : public VNVisitor {
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bool m_allowXUnique = true; // Allow unique assignments
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VDouble0 m_statUnkVars; // Statistic tracking
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V3UniqueNames m_lvboundNames; // For generating unique temporary variable names
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V3UniqueNames m_xrandNames; // For generating unique temporary variable names
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std::unique_ptr<V3UniqueNames> m_xrandNames; // For generating unique temporary variable names
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// METHODS
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@ -141,14 +142,16 @@ class UnknownVisitor final : public VNVisitor {
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VL_RESTORER(m_modp);
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VL_RESTORER(m_constXCvt);
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VL_RESTORER(m_allowXUnique);
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auto xrandNames = std::make_unique<V3UniqueNames>(m_xrandPrefix);
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{
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m_modp = nodep;
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m_constXCvt = true;
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// Class X randomization causes Vxrand in strange places, so disable
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if (VN_IS(nodep, Class)) m_allowXUnique = false;
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m_lvboundNames.reset();
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m_xrandNames.reset();
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xrandNames.swap(m_xrandNames);
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iterateChildren(nodep);
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xrandNames.swap(m_xrandNames);
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}
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}
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void visit(AstAssignDly* nodep) override {
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@ -345,7 +348,7 @@ class UnknownVisitor final : public VNVisitor {
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// We use the special XTEMP type so it doesn't break pure functions
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UASSERT_OBJ(m_modp, nodep, "X number not under module");
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AstVar* const newvarp
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= new AstVar{nodep->fileline(), VVarType::XTEMP, m_xrandNames.get(nodep),
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= new AstVar{nodep->fileline(), VVarType::XTEMP, m_xrandNames->get(nodep),
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VFlagLogicPacked{}, nodep->width()};
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newvarp->lifetime(VLifetime::STATIC);
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++m_statUnkVars;
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@ -517,7 +520,7 @@ public:
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// CONSTRUCTORS
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explicit UnknownVisitor(AstNetlist* nodep)
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: m_lvboundNames{"__Vlvbound"}
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, m_xrandNames{"__Vxrand"} {
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, m_xrandNames{std::make_unique<V3UniqueNames>(m_xrandPrefix)} {
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iterate(nodep);
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}
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~UnknownVisitor() override { //
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@ -525,6 +528,8 @@ public:
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}
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};
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const std::string UnknownVisitor::m_xrandPrefix = "__Vxrand";
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//######################################################################
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// Unknown class functions
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18
test_regress/t/t_user_type_xassign.py
Executable file
18
test_regress/t/t_user_type_xassign.py
Executable file
@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile()
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test.execute()
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test.passes()
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43
test_regress/t/t_user_type_xassign.v
Normal file
43
test_regress/t/t_user_type_xassign.v
Normal file
@ -0,0 +1,43 @@
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// DESCRIPTION: Verilator: Demonstrate complex user typea problem with --x-assign
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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typedef logic [31:0] int_t;
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typedef int_t [6:0] bar_t;
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bar_t the_bar;
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logic [31:0] thing_one;
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always_comb begin
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for (int sel = 0; sel < 1; sel++)
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thing_one = the_bar[sel];
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end
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virtual class SomeClass;
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static function logic compare(int a, int b);
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return a > b;
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endfunction
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endclass
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logic [31:0] thing_two;
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always_comb begin
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for (int sel_a = 0; sel_a < 1; sel_a++)
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thing_two = the_bar[sel_a];
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end
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// finish report
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always @ (posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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