From 7698af5178a3fc492798d9c5d49b24d1caaf49c6 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 14 Nov 2015 20:53:36 -0500
Subject: [PATCH] Tests

---
 test_regress/t/t_interface_gen5_noinl.pl | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100755 test_regress/t/t_interface_gen5_noinl.pl

diff --git a/test_regress/t/t_interface_gen5_noinl.pl b/test_regress/t/t_interface_gen5_noinl.pl
new file mode 100755
index 000000000..1e8c1b963
--- /dev/null
+++ b/test_regress/t/t_interface_gen5_noinl.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+top_filename("t/t_interface_gen5.v");
+
+compile (
+    v_flags2 => ["-Oi"],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;