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verilator_gantt: Fix argument report omitting last digits

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This commit is contained in:
Wilson Snyder 2021-09-24 21:11:15 -04:00
parent 33650336f5
commit 741bb5328e
3 changed files with 3 additions and 5 deletions
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4
bin/verilator_gantt
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@ -36,8 +36,8 @@ def read_data(filename):
re_eval = re.compile(r'^VLPROF eval\sstart\s(\d+)\selapsed\s(\d+)') re_eval = re.compile(r'^VLPROF eval\sstart\s(\d+)\selapsed\s(\d+)')
re_loop = re.compile( re_loop = re.compile(
r'^VLPROF eval_loop\sstart\s(\d+)\selapsed\s(\d+)') r'^VLPROF eval_loop\sstart\s(\d+)\selapsed\s(\d+)')
re_arg1 = re.compile(r'VLPROF arg\s+(\S+)\+([0-9.])\s*') re_arg1 = re.compile(r'VLPROF arg\s+(\S+)\+([0-9.]*)\s*')
re_arg2 = re.compile(r'VLPROF arg\s+(\S+)\s+([0-9.])\s*$') re_arg2 = re.compile(r'VLPROF arg\s+(\S+)\s+([0-9.]*)\s*$')
re_stat = re.compile(r'VLPROF stat\s+(\S+)\s+([0-9.]+)') re_stat = re.compile(r'VLPROF stat\s+(\S+)\s+([0-9.]+)')
re_time = re.compile(r'rdtsc time = (\d+) ticks') re_time = re.compile(r'rdtsc time = (\d+) ticks')
re_proc_cpu = re.compile(r'VLPROFPROC processor\s*:\s*(\d+)\s*$') re_proc_cpu = re.compile(r'VLPROFPROC processor\s*:\s*(\d+)\s*$')

2
src/V3Hasher.cpp
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@ -81,7 +81,7 @@ private:
virtual void visit(AstNode* nodep) override { virtual void visit(AstNode* nodep) override {
#if VL_DEBUG #if VL_DEBUG
UINFO(0, "%Warning: Hashing node as AstNode: " << nodep); UINFO(0, "%Warning: Hashing node as AstNode: " << nodep << endl);
#endif #endif
m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() {}); m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() {});
} }

2
test_regress/t/t_gantt.pl
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@ -8,8 +8,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0. # Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
use IO::File;
# Test for bin/verilator_gantt, # Test for bin/verilator_gantt,
# #
# Only needed in multithreaded regression. # Only needed in multithreaded regression.