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Fix gate optimization out of memory, add --gate-stmts, bug1260.
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@ -4,6 +4,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
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* Verilator 3.919 devel
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**** Fix gate optimization out of memory, add --gate-stmts, bug1260. [Alex Solomatnikov]
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**** Fix compile error on public real parameters by suppressing, bug1261. [Alex Solomatnikov]
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**** Fix input-only tristate comparisons, bug1267. [Alexis G]
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@ -289,6 +289,7 @@ descriptions in the next sections for more information.
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--getenv <var> Get environment variable with defaults
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--help Display this help
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-I<dir> Directory to search for includes
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--gate-stmts <value> Tune gate optimizer depth
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--if-depth <value> Tune IFDEPTH warning
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+incdir+<dir> Directory to search for includes
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--inhibit-sim Create function to turn off sim
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@ -750,6 +751,11 @@ them properly, e.g. as -GSTR="\"My String\"" or -GSTR='"My String"'.
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=back
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=item --gate-stmts I<value>
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Rarely needed. Set the maximum number of statements that may be present in
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an equation for the gate substitution optimization to inline that equation.
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=item --gdb
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Run Verilator underneath an interactive GDB (or VERILATOR_GDB environment
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@ -195,6 +195,7 @@ private:
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bool m_buffersOnly; // Set when we only allow simple buffering, no equations (for clocks)
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AstNodeVarRef* m_lhsVarRef; // VarRef on lhs of assignment (what we're replacing)
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bool m_dedupe; // Set when we use isGateDedupable instead of isGateOptimizable
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int m_ops; // Operation count
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// METHODS
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void clearSimple(const char* because) {
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@ -205,6 +206,7 @@ private:
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}
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// VISITORS
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virtual void visit(AstNodeVarRef* nodep) {
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++m_ops;
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nodep->iterateChildren(*this);
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// We only allow a LHS ref for the var being set, and a RHS ref for something else being read.
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if (nodep->varScopep()->varp()->isSc()) {
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@ -254,6 +256,9 @@ private:
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virtual void visit(AstNode* nodep) {
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// *** Special iterator
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if (!m_isSimple) return; // Fastpath
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if (++m_ops > v3Global.opt.gateStmts()) {
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clearSimple("--gate-stmts exceeded");
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}
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if (!(m_dedupe ? nodep->isGateDedupable() : nodep->isGateOptimizable())
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|| !nodep->isPure()
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|| nodep->isBrancher()) {
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@ -270,6 +275,7 @@ public:
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m_buffersOnly = buffersOnly;
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m_lhsVarRef = NULL;
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m_dedupe = dedupe;
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m_ops = 0;
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// Iterate
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nodep->accept(*this);
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// Check results
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@ -327,7 +333,7 @@ private:
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// METHODS
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void iterateNewStmt(AstNode* nodep, const char* nonReducibleReason, const char* consumeReason) {
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if (m_scopep) {
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UINFO(4," STMT "<<nodep<<endl);
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UINFO(5," STMT "<<nodep<<endl);
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// m_activep is null under AstCFunc's, that's ok.
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m_logicVertexp = new GateLogicVertex(&m_graph, m_scopep, nodep, m_activep, m_inSlow);
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if (nonReducibleReason) {
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@ -787,6 +787,10 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
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else if ( !strncmp (sw, "-G", strlen("-G"))) {
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addParameter(string (sw+strlen("-G")), false);
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}
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else if ( !strcmp (sw, "-gate-stmts") && (i+1)<argc ) {
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shift;
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m_gateStmts = atoi(argv[i]);
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}
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else if ( !strcmp (sw, "-getenv") && (i+1)<argc ) {
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shift;
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cout<<V3Options::getenvBuiltins(argv[i])<<endl;
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@ -1252,6 +1256,7 @@ V3Options::V3Options() {
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m_convergeLimit = 100;
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m_dumpTree = 0;
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m_gateStmts = 100;
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m_ifDepth = 0;
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m_inlineMult = 2000;
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m_moduleRecursion = 100;
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@ -107,6 +107,7 @@ class V3Options {
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int m_convergeLimit;// main switch: --converge-limit
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int m_dumpTree; // main switch: --dump-tree
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int m_gateStmts; // main switch: --gate-stmts
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int m_ifDepth; // main switch: --if-depth
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int m_inlineMult; // main switch: --inline-mult
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int m_moduleRecursion;// main switch: --module-recursion-depth
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@ -254,6 +255,7 @@ class V3Options {
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int convergeLimit() const { return m_convergeLimit; }
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int dumpTree() const { return m_dumpTree; }
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int gateStmts() const { return m_gateStmts; }
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int ifDepth() const { return m_ifDepth; }
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int inlineMult() const { return m_inlineMult; }
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int moduleRecursionDepth() const { return m_moduleRecursion; }
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56
test_regress/t/t_gate_chained.pl
Executable file
56
test_regress/t/t_gate_chained.pl
Executable file
@ -0,0 +1,56 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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use IO::File;
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sub gen {
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my $filename = shift;
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my $fh = IO::File->new(">$filename");
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$fh->print("// Generated by t_gate_chained.pl\n");
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$fh->print("module t (clk,i,sel,o);\n");
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$fh->print(" input clk;\n");
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$fh->print(" input [63:0] i;\n");
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$fh->print(" input [15:0] sel;\n");
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$fh->print(" output [63:0] o;\n");
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$fh->print("\n");
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my $prev = "i";
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my $n = 9000;
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for (my $i=1; $i<$n; ++$i) {
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$fh->printf(" wire [63:0] ass%04x = (sel == 16'h%04x) ? 64'h0 : $prev;\n", $i, $i);
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$prev = sprintf("ass%04x", $i);
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}
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$fh->print("\n");
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$fh->print(" wire [63:0] o = $prev;\n");
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$fh->print("\n");
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$fh->print(" always @ (posedge clk) begin\n");
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$fh->print(' $write("*-* All Finished *-*\n");',"\n");
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$fh->print(' $finish;',"\n");
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$fh->print(" end\n");
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$fh->print("endmodule\n");
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}
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top_filename("$Self->{obj_dir}/t_gate_chained.v");
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gen($Self->{top_filename});
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compile (
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verilator_flags2=>["--stats --x-assign fast --x-initial fast"],
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);
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execute (
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check_finished=>1,
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);
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# Must be <<9000 above to prove this worked
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file_grep ($Self->{stats}, qr/Optimizations, Gate sigs deleted\s+(\d+)/i, 8575);
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ok(1);
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1;
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