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Fix 'for' loop with outside variable reference (#4660).

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Wilson Snyder 2023-11-11 14:47:54 -05:00
parent 4286af3599
commit 706534ffe1
4 changed files with 53 additions and 8 deletions
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@ -31,6 +31,7 @@ Verilator 5.019 devel
* Fix MingW compilation (#4675). [David Ledger]
* Fix trace when using SystemC with certain configurations (#4676). [Anthony Donlon]
* Fix C++20 compilation errors (#4670).
* Fix 'for' loop with outside variable reference (#4660). [David Harris]
Verilator 5.018 2023-10-30

17
src/V3Simulate.h
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@ -669,14 +669,15 @@ private:
iterateChildrenConst(nodep);
} else {
iterateConst(nodep->condp());
if (optimizable()) {
if (fetchConst(nodep->condp())->num().isNeqZero()) {
iterateConst(nodep->thenp());
newValue(nodep, fetchValue(nodep->thenp()));
} else {
iterateConst(nodep->elsep());
newValue(nodep, fetchValue(nodep->elsep()));
}
if (!optimizable()) return;
if (fetchConst(nodep->condp())->num().isNeqZero()) {
iterateConst(nodep->thenp());
if (!optimizable()) return;
newValue(nodep, fetchValue(nodep->thenp()));
} else {
iterateConst(nodep->elsep());
if (!optimizable()) return;
newValue(nodep, fetchValue(nodep->elsep()));
}
}
}

17
test_regress/t/t_unroll_unopt_io.pl Executable file
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@ -0,0 +1,17 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2023 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
);
ok(1);
1;

26
test_regress/t/t_unroll_unopt_io.v Normal file
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@ -0,0 +1,26 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Outputs
zeros,
// Inputs
num
);
parameter WIDTH = 1;
input logic [WIDTH-1:0] num;
output logic [$clog2(WIDTH+1)-1:0] zeros;
integer i;
always_comb begin
i = 0;
while ((i < WIDTH) & ~num[WIDTH-1-i]) i = i + 1;
zeros = i[$clog2(WIDTH+1) - 1 : 0];
end
endmodule