Tests: Cover some internal code coverage issues

src/V3Const.cpp

@@ -703,14 +703,14 @@ private:
         }
         if (newp) {
             UINFO(4, "Transformed leaf of bit tree to " << newp << std::endl);
-            if (debug() >= 9) {
+            if (debug() >= 9) {  // LCOV_EXCL_START
                 static int c = 0;
                 std::cout << "Call matchBitOpTree[" << c << "]\n";
                 nodep->dumpTree(std::cout);
                 std::cout << "\nResult:\n";
                 newp->dumpTree(std::cout);
                 ++c;
-            }
+            }  // LCOV_EXCL_STOP
             nodep->replaceWith(newp);
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
         }

src/V3LinkDot.cpp

@@ -2452,8 +2452,9 @@ private:
                 // Generally set by parse, but might be an import
                 nodep->classOrPackagep(foundp->classOrPackagep());
             }
-            if (!nodep->varp()) {
-                nodep->v3error("Can't find definition of signal, again: " << nodep->prettyNameQ());
+            if (VL_UNCOVERABLE(!nodep->varp())) {
+                nodep->v3error("Can't find definition of signal, again: "  // LCOV_EXCL_LINE
+                               << nodep->prettyNameQ());
             }
         }
     }

src/V3PreLex.l

@@ -348,7 +348,8 @@ void V3PreLex::pushStateIncFilename() {
 }
 
 void V3PreLex::debug(int level) {
-    yy_flex_debug = level; }
+    yy_flex_debug = level;  // Use --debugi-V3PreShell, if level<5 this level is 0
+}
 int V3PreLex::debug() {
     return yy_flex_debug; }
 
@@ -396,8 +397,8 @@ again:
         string forceOut = endOfStream(again /*ref*/);
         streamp = curStreamp();  // May have been updated
         if (forceOut != "") {
-            if (forceOut.length() > max_size) {
-                yyerrorf("Output buffer too small for a `line");
+            if (forceOut.length() > max_size) {  // LCOV_EXCL_LINE
+                yyerrorf("Output buffer too small for a `line");  // LCOV_EXCL_LINE
             } else {
                 got = forceOut.length();
                 strncpy(buf, forceOut.c_str(), got);

src/V3PreProc.cpp

@@ -272,7 +272,7 @@ public:
         m_lexp->m_keepComments = keepComments();
         m_lexp->m_keepWhitespace = keepWhitespace();
         m_lexp->m_pedantic = pedantic();
-        m_lexp->debug(debug() >= 5 ? debug() : 0);  // See also V3PreProc::debug() method
+        debug(debug());  // Set lexer debug via V3PreProc::debug() method
     }
     ~V3PreProcImp() override {
         if (m_lexp) VL_DO_CLEAR(delete m_lexp, m_lexp = nullptr);
@@ -486,6 +486,12 @@ void V3PreProcImp::comment(const string& text) {
 //*************************************************************************
 // VPreProc Methods.
 
+void V3PreProc::debug(int level) {
+    m_debug = level;
+    V3PreProcImp* idatap = static_cast<V3PreProcImp*>(this);
+    if (idatap->m_lexp) idatap->m_lexp->debug(debug() >= 5 ? debug() : 0);
+}
+
 FileLine* V3PreProc::fileline() {
     V3PreProcImp* idatap = static_cast<V3PreProcImp*>(this);
     return idatap->m_lexp->m_tokFilelinep;

src/V3PreProc.h

@@ -61,7 +61,7 @@ public:
     virtual void insertUnreadback(const string& text) = 0;
 
     int debug() const { return m_debug; }
-    void debug(int level) { m_debug = level; }
+    void debug(int level);
 
     FileLine* fileline();  ///< File/Line number for last getline call
 

test_regress/t/t_dist_error_format.pl

@@ -39,7 +39,8 @@ sub formats {
             foreach my $line (split /\n/, $wholefile) {
                 ++$lineno;
                 $line =~ s/(\$display|\$write).*\".*%(Error|Warning)//;
-                if ($line =~ /(Error|Warning)/) {
+                if ($line =~ /(Error|Warning)/
+                    && $line !~ /Error-internal-contents-bad/) {
                     # These formats are documented in bin/verilator
                     # Error with fileline
                     # For testing only: we assume no : in filename

test_regress/t/t_math_pow2.v

@@ -17,7 +17,8 @@ module t (/*AUTOARG*/
    // Aggregate outputs into a single result vector
    //wire [31:0] 	pow32b = {24'h0,crc[15:8]}**crc[7:0];  // Overflows
    wire [3:0] 	pow4b = crc[7:4] ** crc[3:0];
-   wire [63:0] 	result = {60'h0, pow4b};
+   wire [31:0] 	pow2 = 2 ** crc[3:0];  // Optimizes to shift
+   wire [63:0] 	result = {pow2, 28'h0, pow4b};
 
    // Test loop
    always @ (posedge clk) begin
@@ -40,8 +41,7 @@ module t (/*AUTOARG*/
       else if (cyc==99) begin
 	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
 	 if (crc !== 64'hc77bb9b3784ea091) $stop;
-	 // What checksum will we end up with (above print should match)
-`define EXPECTED_SUM 64'h1fec4b2b71cf8024
+`define EXPECTED_SUM 64'h056ea1c5a63aff6a
 	 if (sum !== `EXPECTED_SUM) $stop;
 	 $write("*-* All Finished *-*\n");
 	 $finish;

test_regress/t/t_preproc_debugi.pl

@@ -0,0 +1,27 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+# Hit the debug statements in the preprocessor for internal coverage
+
+run(cmd => ["../bin/verilator",
+            "-E",
+            "t/t_preproc_debugi.v",
+            "--debug",
+            "--debugi-V3PreShell 10",
+    ],
+    tee => $Self->{verbose},
+    logfile => "$Self->{obj_dir}/sim.log",
+    verilator_run => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_preproc_debugi.v

@@ -0,0 +1,10 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2009 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define FOO
+`define BAR(aa,bb) aa bb
+`FOO
+`BAR(aa,bb)

test_regress/t/t_preproc_eof1_bad.out

@@ -0,0 +1,2 @@
+%Error: t/t_preproc_eof1_bad.v:9:1: EOF in '/* ... */' block comment
+%Error: Exiting due to

test_regress/t/t_preproc_eof1_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_preproc_eof1_bad.v

@@ -0,0 +1,7 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2019 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+/*

test_regress/t/t_preproc_eof2_bad.out

@@ -0,0 +1,2 @@
+%Error: t/t_preproc_eof2_bad.v:10:1: Unterminated ( in define formal arguments.
+%Error: Exiting due to

test_regress/t/t_preproc_eof2_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_preproc_eof2_bad.v

@@ -0,0 +1,7 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2019 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define FOO(a,

test_regress/t/t_preproc_eof3_bad.out

@@ -0,0 +1,7 @@
+%Error: t/t_preproc_eof3_bad.v:10:1: EOF in define argument list
+   10 | %Error-internal-contents-bad-ct2-ln10
+      | ^
+%Error: t/t_preproc_eof3_bad.v:10:1: Expecting ) or , to end argument list for define reference. Found: EOF
+   10 | %Error-internal-contents-bad-ct2-ln10
+      | ^
+%Error: Exiting due to

test_regress/t/t_preproc_eof3_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_preproc_eof3_bad.v

@@ -0,0 +1,8 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2019 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define FOO(a,b)
+`FOO(1,

test_regress/t/t_preproc_eof4_bad.out

@@ -0,0 +1,2 @@
+%Error: t/t_preproc_eof4_bad.v:8:1: Unterminated string
+%Error: Exiting due to

test_regress/t/t_preproc_eof4_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_preproc_eof4_bad.v

@@ -0,0 +1,7 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2019 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+"blah

test_regress/t/t_verilated_debug.out

@@ -8,6 +8,8 @@ internalsDump:
 -V{t#,#}+++++TOP Evaluate Vt_verilated_debug::eval
 -V{t#,#}+    Vt_verilated_debug::_eval_debug_assertions
 -V{t#,#}+    Vt_verilated_debug::_eval_initial
+-V{t#,#}+    Vt_verilated_debug::_initial__TOP__1
+  Data: w96: 000000aa 000000bb 000000cc 
 -V{t#,#}+    Vt_verilated_debug::_eval_settle
 -V{t#,#}+    Vt_verilated_debug::_eval
 -V{t#,#}+    Vt_verilated_debug::_change_request
@@ -20,7 +22,7 @@ internalsDump:
 -V{t#,#}+    Vt_verilated_debug::_eval_debug_assertions
 -V{t#,#}+ Clock loop
 -V{t#,#}+    Vt_verilated_debug::_eval
--V{t#,#}+    Vt_verilated_debug::_sequent__TOP__1
+-V{t#,#}+    Vt_verilated_debug::_sequent__TOP__2
 *-* All Finished *-*
 -V{t#,#}+    Vt_verilated_debug::_change_request
 -V{t#,#}+    Vt_verilated_debug::_change_request_1

test_regress/t/t_verilated_debug.v

@@ -11,6 +11,14 @@ module t (/*AUTOARG*/
 
    input clk;
 
+   reg [95:0] wide;
+
+   initial begin
+      // internal code coverage for _vl_debug_print_w
+      wide = {32'haa, 32'hbb, 32'hcc};
+      $c("_vl_debug_print_w(",$bits(wide),",",wide,");");
+   end
+
    // Test loop
    always @ (posedge clk) begin
       $write("*-* All Finished *-*\n");

test_regress/t/t_wire_self_bad.out

@@ -0,0 +1,4 @@
+%Error: t/t_wire_self_bad.v:11:16: Wire inputs its own output, creating circular logic (wire x=x)
+   11 |    wire myself = myself;
+      |                ^
+%Error: Exiting due to

test_regress/t/t_wire_self_bad.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    verilator_flags2 => ["--lint-only --language 1800-2017"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_wire_self_bad.v

@@ -0,0 +1,13 @@
+// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
+//
+// Simple bi-directional alias test.
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+
+   wire myself = myself;
+
+endmodule

test_regress/t/t_wrapper_legacy.cpp

@@ -81,8 +81,8 @@ int main(int argc, char** argv, char** env) {
     CHECK_RESULT_CSTR(Verilated::productName(), Verilated::productName());
     CHECK_RESULT_CSTR(Verilated::productVersion(), Verilated::productVersion());
 
-    if (Verilated::timeunit()) {}
-    if (Verilated::timeprecision()) {}
+    CHECK_RESULT(Verilated::timeunit(), 12);
+    CHECK_RESULT(Verilated::timeprecision(), 12);
 
     VM_PREFIX* topp = new VM_PREFIX();