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Add unsigned keyword

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git-svn-id: file://localhost/svn/verilator/trunk/verilator@919 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2007-05-12 15:31:04 +00:00
parent 8d56b498d1
commit 6f414ee9e2
3 changed files with 18 additions and 16 deletions
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6
src/flexfix
View File

@ -19,7 +19,7 @@
#
######################################################################
# DESCRIPTION: Edits flex output to get around Redhat 8.0 broken flex.
# DESCRIPTION: Edits flex output to get around various broken flex issues.
foreach my $line (<STDIN>) {
# Fix flex 2.5.4 namespace omission
@ -28,5 +28,9 @@ foreach my $line (<STDIN>) {
$line =~ s!(\#define\s+yyFlexLexer\s+yyFlexLexer)!//flexfix: $1!g;
# Fix flex 2.5.1 yytext_ptr undef
$line =~ s!(\#undef\s+yytext_ptr)!//flexfix: $1!g;
# Fix flex 2.5.4 and GCC 4.1.0 warn_unused_result
$line =~ s!\(void\) *fwrite\((.*)\)!if (fwrite($1)) {}!g;
# Fix flex 2.5.33 and GCC 4.1.2 "warning: comparison between signed and unsigned integer expressions" in YY_INPUT
$line =~ s!for \( n = 0; n < max_size && !for ( n = 0; ((size_t)n < (size_t)max_size) && !g;
print "$line";
}

2
src/verilog.l
View File

@ -278,6 +278,7 @@ escid \\[^ \t\f\r\n]+
"genvar" {yylval.fileline = CRELINE(); return yGENVAR;}
"localparam" {yylval.fileline = CRELINE(); return yLOCALPARAM;}
"signed" {yylval.fileline = CRELINE(); return ySIGNED;}
"unsigned" {yylval.fileline = CRELINE(); return yUNSIGNED;}
/* Special errors */
"include" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented; probably you want `include instead: %s",yytext);}
/* Generic unsupported warnings */
@ -295,7 +296,6 @@ escid \\[^ \t\f\r\n]+
"pulsestyle_ondetect" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
"pulsestyle_onevent" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
"showcancelled" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
"unsigned" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
"use" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
}

26
src/verilog.y
View File

@ -93,8 +93,6 @@ AstCase* V3Parse::s_caseAttrp = NULL;
//======================================================================
class AstSenTree;
# define NEW_SENTREE_BRANCH(a,b) (new AstSenTree((a),(b)))
%}
%union {
@ -115,6 +113,8 @@ class AstSenTree;
AstFunc* funcp;
AstFuncRef* funcrefp;
AstModule* modulep;
AstNodeVarRef* varnodep;
AstParseRef* parserefp;
AstPin* pinp;
AstRange* rangep;
AstSenItem* senitemp;
@ -122,8 +122,6 @@ class AstSenTree;
AstTaskRef* taskrefp;
AstVar* varp;
AstVarRef* varrefp;
AstNodeVarRef* varnodep;
AstParseRef* parserefp;
}
%token<nump> yINTNUM
@ -136,7 +134,7 @@ class AstSenTree;
%token<fileline> yGENVAR yGENERATE yENDGENERATE
%token<fileline> ySPECIFY yENDSPECIFY yTIMINGSPEC
%token<fileline> yCASE yCASEX yCASEZ yDEFAULT yENDCASE yIF yELSE
%token<fileline> yASSIGN yINTEGER yFOR ySUPPLY0 ySUPPLY1 ySIGNED
%token<fileline> yASSIGN yINTEGER yFOR ySUPPLY0 ySUPPLY1 ySIGNED yUNSIGNED
%token<fileline> yBUF yNOT yAND yNAND yNOR yXOR yXNOR
%token<fileline> ySCALARED yVECTORED
@ -236,7 +234,7 @@ class AstSenTree;
%type<nodep> v2kPortList v2kPortSig
%type<nodep> v2kPort ioDecl varDecl
%type<nodep> modParDecl modParList modParE
%type<nodep> modItem modItemList modItemListOrNone modOrGenItem
%type<nodep> modItem modItemList modItemListE modOrGenItem
%type<nodep> genItem genItemList genItemBegin genItemBlock genTopBlock genCaseList
%type<nodep> dterm
%type<varp> onesig sigId sigIdRange paramId sigList regsig regsigList regSigId
@ -301,11 +299,11 @@ statePop: { V3Read::statePop(); }
//**********************************************************************
// Modules
file: prog
| file prog
file: mod
| file mod
;
prog: mheader modParE modportsE ';' modItemListOrNone yENDMODULE
mod: mheader modParE modportsE ';' modItemListE yENDMODULE
{ $1->modTrace(V3Parse::s_trace); // Stash for implicit wires, etc
if ($2) $1->addStmtp($2); if ($3) $1->addStmtp($3); if ($5) $1->addStmtp($5); }
;
@ -375,6 +373,7 @@ varInout: yINOUT { VARIO(INOUT); }
varSignedE: /*empty*/ { }
| ySIGNED { VARSIGNED(true); }
| yUNSIGNED { VARSIGNED(false); }
;
v2kNetDeclE: /*empty*/ { }
@ -408,7 +407,7 @@ modParDecl: varRESET varGParam varSignedE regrangeE paramList { $$ = $5; }
//************************************************
// modItemList
modItemListOrNone: { $$ = NULL; }
modItemListE: /* empty */ { $$ = NULL; }
| modItemList { $$ = $1; }
;
@ -594,8 +593,7 @@ portrangeE: /* empty */ { $$ = NULL; }
;
// Parameters
param: paramId '=' expr { $$ = $1; $$->initp($3); }
| paramId sigAttrList '=' expr { $$ = $1; $$->initp($4); }
param: paramId sigAttrListE '=' expr { $$ = $1; $$->initp($4); }
;
paramList: param { $$ = $1; }
@ -637,8 +635,8 @@ cellpinitemE: /* empty */ { $$ = NULL; V3Parse::s_pinNum++; }
;
sensitivityE: /* empty */ { $$ = NULL; }
| '@' '(' senList ')' { $$ = NEW_SENTREE_BRANCH($1,$3); }
| '@' senitem { $$ = NEW_SENTREE_BRANCH($1,$2); }
| '@' '(' senList ')' { $$ = new AstSenTree($1,$3); }
| '@' senitem { $$ = new AstSenTree($1,$2); }
| '@' '(' '*' ')' { $$ = NULL; $2->v3error("Use @*. always @ (*) to be depreciated in Verilog 2005.\n"); }
| '@' '*' { $$ = NULL; } /* Verilog 2001 */
;