diff --git a/bin/verilator b/bin/verilator
index e685664d7..3f921dc02 100755
--- a/bin/verilator
+++ b/bin/verilator
@@ -4075,9 +4075,10 @@ is ignored, only a single trace file may be active at once.
 $dumpall/$dumpportsall, $dumpon/$dumpportson, $dumpoff/$dumpportsoff, and
 $dumplimit/$dumpportlimit are currently ignored.
 
-=item $finish, $stop
+=item $exit, $finish, $stop
 
-The rarely used optional parameter to $finish and $stop is ignored.
+The rarely used optional parameter to $finish and $stop is ignored. $exit
+is aliased to $finish.
 
 =item $fopen, $fclose, $fdisplay, $ferror, $feof, $fflush, $fgetc, $fgets,
 $fscanf, $fwrite, $fscanf, $sscanf
diff --git a/src/verilog.l b/src/verilog.l
index a357f122c..0b7301475 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -191,6 +191,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   "$dumpportsoff"       { FL; return yD_DUMPOFF; }
   "$dumpportson"        { FL; return yD_DUMPON; }
   "$dumpvars"           { FL; return yD_DUMPVARS; }
+  "$exit"               { FL; return yD_EXIT; }
   "$exp"                { FL; return yD_EXP; }
   "$fclose"             { FL; return yD_FCLOSE; }
   "$fdisplay"           { FL; return yD_FDISPLAY; }
diff --git a/src/verilog.y b/src/verilog.y
index ef4e4a045..4c6a9c5a4 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -724,6 +724,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
 %token<fl>              yD_DUMPPORTS    "$dumpports"
 %token<fl>              yD_DUMPVARS     "$dumpvars"
 %token<fl>              yD_ERROR        "$error"
+%token<fl>              yD_EXIT         "$exit"
 %token<fl>              yD_EXP          "$exp"
 %token<fl>              yD_FATAL        "$fatal"
 %token<fl>              yD_FCLOSE       "$fclose"
@@ -3553,6 +3554,8 @@ system_t_call<nodep>:		// IEEE: system_tf_call (as task)
 	|	yD_C '(' cStrList ')'			{ $$ = (v3Global.opt.ignc() ? nullptr : new AstUCStmt($1,$3)); }
 	|	yD_SYSTEM '(' expr ')'			{ $$ = new AstSystemT($1, $3); }
 	//
+	|	yD_EXIT parenE				{ $$ = new AstFinish($1); }
+	//
 	|	yD_FCLOSE '(' idClassSel ')'		{ $$ = new AstFClose($1, $3); }
 	|	yD_FFLUSH parenE			{ $$ = new AstFFlush($1, nullptr); }
 	|	yD_FFLUSH '(' expr ')'			{ $$ = new AstFFlush($1, $3); }
diff --git a/test_regress/t/t_exit.pl b/test_regress/t/t_exit.pl
new file mode 100755
index 000000000..9a15dd2cc
--- /dev/null
+++ b/test_regress/t/t_exit.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_exit.v b/test_regress/t/t_exit.v
new file mode 100644
index 000000000..6dd666415
--- /dev/null
+++ b/test_regress/t/t_exit.v
@@ -0,0 +1,12 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+program t(/*AUTOARG*/);
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $exit;  // Must be in program block
+   end
+endprogram