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Internals: Indent verilated_std.sv with Verilog-mode. No functional change.

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This commit is contained in:
Wilson Snyder 2023-04-06 21:27:16 -04:00
parent 8caf9be3e6
commit 6c21b21ecc
1 changed files with 72 additions and 72 deletions
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16
include/verilated_std.sv
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@ -43,11 +43,11 @@ package std;
endfunction
task put(T message);
`ifdef VERILATOR_TIMING
`ifdef VERILATOR_TIMING
if (m_bound != 0)
wait (m_queue.size() < m_bound);
m_queue.push_back(message);
`endif
`endif
endtask
function int try_put(T message);
@ -59,10 +59,10 @@ package std;
endfunction
task get(ref T message);
`ifdef VERILATOR_TIMING
`ifdef VERILATOR_TIMING
wait (m_queue.size() > 0);
message = m_queue.pop_front();
`endif
`endif
endtask
function int try_get(ref T message);
@ -74,10 +74,10 @@ package std;
endfunction
task peek(ref T message);
`ifdef VERILATOR_TIMING
`ifdef VERILATOR_TIMING
wait (m_queue.size() > 0);
message = m_queue[0];
`endif
`endif
endtask
function int try_peek(ref T message);
@ -101,10 +101,10 @@ package std;
endfunction
task get(int keyCount = 1);
`ifdef VERILATOR_TIMING
`ifdef VERILATOR_TIMING
wait (m_keyCount >= keyCount);
m_keyCount -= keyCount;
`endif
`endif
endtask
function int try_get(int keyCount = 1);