Internals: Indent verilated_std.sv with Verilog-mode. No functional change.

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Wilson Snyder 2023-04-06 21:27:16 -04:00

parent 8caf9be3e6

commit 6c21b21ecc

1 changed files with 72 additions and 72 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

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