Tests: Add t_include_all. Fix GCC warning when DPI with VPI.

include/verilated_dpi.cpp

@@ -30,7 +30,9 @@
 
 // On MSVC++ we need svdpi.h to declare exports, not imports
 #define DPI_PROTOTYPES
+#undef XXTERN
 #define XXTERN DPI_EXTERN DPI_DLLESPEC
+#undef EETERN
 #define EETERN DPI_EXTERN DPI_DLLESPEC
 
 #include "vltstd/svdpi.h"

include/vltstd/vpi_user.h

@@ -105,10 +105,12 @@ typedef unsigned char    PLI_UBYTE8;
 
 /* object is defined imported by the application */
 
+#undef XXTERN
 #define XXTERN PLI_EXTERN PLI_DLLISPEC
 
 /* object is exported by the application */
 
+#undef EETERN
 #define EETERN PLI_EXTERN PLI_DLLESPEC
 #endif
 

test_regress/t/t_include_all.pl

@@ -0,0 +1,44 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+my $root = "..";
+
+compile (
+    # Can't use --coverage and --savable together, so cheat and compile inline
+    verilator_flags2 => ['--cc --coverage-toggle --coverage-line --coverage-user --trace --vpi $root/include/verilated_save.cpp'],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+my %hit;
+foreach my $file (glob("$root/include/*.cpp $root/include/*.h")) {
+    $file =~ s!.*/!!;
+    print "NEED: $file\n" if $Self->{verbose};
+    $hit{$file} = 0;
+}
+foreach my $dfile (glob("$Self->{obj_dir}/*.d")) {
+    my $wholefile = file_contents($dfile);
+    foreach my $file (split /\s+/, $wholefile) {
+        $file =~ s!.*/!!;
+        print "USED: $file\n" if $Self->{verbose};
+        $hit{$file} = 1;
+    }
+}
+
+foreach my $file (sort keys %hit) {
+    if (!$hit{$file}
+        && $file !~ /_sc/) {
+        $Self->error("Include file not covered by t_include_all test: ",$file);
+    }
+}
+
+ok(1);
+1;

test_regress/t/t_include_all.v

@@ -0,0 +1,31 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   integer cyc;
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc!=0) begin
+         if (cyc==10) begin
+            $write("*-* All Finished *-*\n");
+            $finish;
+         end
+      end
+   end
+
+   cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
+
+   export "DPI-C" function dpix_f_int;
+   function int dpix_f_int ();
+      return cyc;
+   endfunction
+endmodule