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Set FST timescale correctly. (#2266)
The FST trace timescale used to be set in the constructor via set_time_unit, but at that point we haven't normally opened the file yet so it was just dropped. On top of that, we actually want to use set_time_resolution... FST trace timescales now match the VCD.
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@ -100,6 +100,7 @@ void VerilatedFst::open(const char* filename) VL_MT_UNSAFE {
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m_assertOne.check();
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m_fst = fstWriterCreate(filename, 1);
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fstWriterSetPackType(m_fst, FST_WR_PT_LZ4);
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fstWriterSetTimescaleFromString(m_fst, m_timeRes.c_str());
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#ifdef VL_TRACE_THREADED
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fstWriterSetParallelMode(m_fst, 1);
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#endif
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@ -65,6 +65,8 @@ private:
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// helpers
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std::vector<char> m_valueStrBuffer;
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std::string m_timeRes;
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public:
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explicit VerilatedFst(void* fst = NULL);
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~VerilatedFst();
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@ -77,11 +79,11 @@ public:
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fstWriterClose(m_fst);
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m_fst = NULL;
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}
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void set_time_unit(const char* unitp) { fstWriterSetTimescaleFromString(m_fst, unitp); }
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void set_time_unit(const char*) {}
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void set_time_unit(const std::string& unit) { set_time_unit(unit.c_str()); }
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void set_time_resolution(const char*) {}
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void set_time_resolution(const std::string& unit) { set_time_resolution(unit.c_str()); }
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void set_time_resolution(const char* unitp) { m_timeRes = unitp; }
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void set_time_resolution(const std::string& unit) { m_timeRes = unit; }
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// double timescaleToDouble(const char* unitp);
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// std::string doubleToTimescale(double value);
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@ -1,12 +1,12 @@
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$date
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Wed Dec 4 07:48:29 2019
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Sun Apr 19 04:13:22 2020
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$end
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$version
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fstWriter
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$end
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$timescale
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1ns
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1ps
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$end
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$scope module top $end
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$var wire 1 ! clk $end
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@ -1,12 +1,12 @@
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$date
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Sun Oct 21 21:57:08 2018
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Sun Apr 19 04:15:23 2020
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$end
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$version
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fstWriter
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$end
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$timescale
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1ns
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1ps
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$end
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$scope module top $end
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$var wire 1 ! clk $end
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@ -1,12 +1,12 @@
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$date
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Sun Apr 12 20:15:55 2020
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Sun Apr 19 04:15:26 2020
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$end
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$version
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fstWriter
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$end
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$timescale
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1ns
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1ps
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$end
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$scope module top $end
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$var wire 1 ! clk $end
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@ -1,12 +1,12 @@
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$date
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Sun Apr 12 20:17:15 2020
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Sun Apr 19 04:15:31 2020
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$end
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$version
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fstWriter
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$end
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$timescale
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1ns
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1ps
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$end
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$scope module top $end
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$var wire 1 ! clk $end
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@ -1,12 +1,12 @@
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$date
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Sun Apr 12 20:14:19 2020
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Sun Apr 19 04:15:33 2020
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$end
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$version
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fstWriter
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$end
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$timescale
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1ns
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1ps
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$end
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$scope module top $end
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$var wire 1 ! clk $end
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@ -1,12 +1,12 @@
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$date
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Sun Apr 12 20:17:58 2020
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Sun Apr 19 04:15:36 2020
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$end
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$version
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fstWriter
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$end
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$timescale
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1ns
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1ps
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$end
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$scope module top $end
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$var wire 1 ! clk $end
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@ -1,12 +1,12 @@
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$date
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Sun Apr 12 20:19:35 2020
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Sun Apr 19 04:15:38 2020
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$end
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$version
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fstWriter
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$end
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$timescale
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1ns
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1ps
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$end
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$scope module top $end
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$var wire 1 ! clk $end
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@ -1,12 +1,12 @@
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$date
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Sat Apr 18 22:18:21 2020
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Sun Apr 19 04:15:48 2020
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$end
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$version
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fstWriter
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$end
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$timescale
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1ns
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1ps
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$end
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$scope module topa $end
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$var wire 1 ! clk $end
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@ -1,12 +1,12 @@
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$date
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Sat Mar 7 18:27:58 2020
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Sun Apr 19 04:15:51 2020
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$end
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$version
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fstWriter
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$end
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$timescale
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1ns
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1ps
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$end
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$scope module topa $end
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$var wire 1 ! clk $end
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@ -1,12 +1,12 @@
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$date
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Sat Apr 18 22:19:21 2020
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Sun Apr 19 04:13:00 2020
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$end
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$version
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fstWriter
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$end
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$timescale
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1ns
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1ps
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$end
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$scope module topa $end
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$var wire 1 ! clk $end
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