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Fix 'output tri0' 2001 declaration; Var characteristics must be attributes

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This commit is contained in:
Wilson Snyder 2012-04-24 07:45:02 -04:00
parent b1507060ad
commit 68046244dd
4 changed files with 34 additions and 9 deletions
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7
src/V3AstNodes.cpp
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@ -75,6 +75,9 @@ bool AstVar::isScBv() const {
} }
void AstVar::combineType(AstVarType type) { void AstVar::combineType(AstVarType type) {
// These flags get combined with the existing settings of the flags.
// We don't test varType for certain types, instead set flags since
// when we combine wires cross-hierarchy we need a union of all characteristics.
if (type == AstVarType::SUPPLY0) type = AstVarType::WIRE; if (type == AstVarType::SUPPLY0) type = AstVarType::WIRE;
if (type == AstVarType::SUPPLY1) type = AstVarType::WIRE; if (type == AstVarType::SUPPLY1) type = AstVarType::WIRE;
m_varType=type; // For debugging prints only m_varType=type; // For debugging prints only
@ -86,6 +89,10 @@ void AstVar::combineType(AstVarType type) {
if (type==AstVarType::INOUT || type==AstVarType::TRIWIRE if (type==AstVarType::INOUT || type==AstVarType::TRIWIRE
|| type==AstVarType::TRI0 || type==AstVarType::TRI1) || type==AstVarType::TRI0 || type==AstVarType::TRI1)
m_tristate = true; m_tristate = true;
if (type==AstVarType::TRI0)
m_isPulldown = true;
if (type==AstVarType::TRI1)
m_isPullup = true;
} }
string AstVar::verilogKwd() const { string AstVar::verilogKwd() const {

6
src/V3AstNodes.h
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@ -639,6 +639,8 @@ private:
bool m_fileDescr:1; // File descriptor bool m_fileDescr:1; // File descriptor
bool m_isConst:1; // Table contains constant data bool m_isConst:1; // Table contains constant data
bool m_isStatic:1; // Static variable bool m_isStatic:1; // Static variable
bool m_isPulldown:1; // Tri0
bool m_isPullup:1; // Tri1
bool m_trace:1; // Trace this variable bool m_trace:1; // Trace this variable
void init() { void init() {
@ -649,7 +651,7 @@ private:
m_sigPublic=false; m_sigModPublic=false; m_sigUserRdPublic=false; m_sigUserRWPublic=false; m_sigPublic=false; m_sigModPublic=false; m_sigUserRdPublic=false; m_sigUserRWPublic=false;
m_funcLocal=false; m_funcReturn=false; m_funcLocal=false; m_funcReturn=false;
m_attrClockEn=false; m_attrScBv=false; m_attrIsolateAssign=false; m_attrSFormat=false; m_attrClockEn=false; m_attrScBv=false; m_attrIsolateAssign=false; m_attrSFormat=false;
m_fileDescr=false; m_isConst=false; m_isStatic=false; m_fileDescr=false; m_isConst=false; m_isStatic=false; m_isPulldown=false; m_isPullup=false;
m_trace=false; m_trace=false;
} }
public: public:
@ -787,6 +789,8 @@ public:
bool isStatic() const { return m_isStatic; } bool isStatic() const { return m_isStatic; }
bool isFuncLocal() const { return m_funcLocal; } bool isFuncLocal() const { return m_funcLocal; }
bool isFuncReturn() const { return m_funcReturn; } bool isFuncReturn() const { return m_funcReturn; }
bool isPullup() const { return m_isPullup; }
bool isPulldown() const { return m_isPulldown; }
bool attrClockEn() const { return m_attrClockEn; } bool attrClockEn() const { return m_attrClockEn; }
bool attrScBv() const { return m_attrScBv; } bool attrScBv() const { return m_attrScBv; }
bool attrFileDescr() const { return m_fileDescr; } bool attrFileDescr() const { return m_fileDescr; }

6
src/V3Tristate.cpp
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@ -589,12 +589,10 @@ class TristateVisitor : public TristateBaseVisitor {
m_varvec.push_back(nodep); m_varvec.push_back(nodep);
nodep->iterateChildren(*this); nodep->iterateChildren(*this);
// If tri0/1 force a pullup // If tri0/1 force a pullup
bool pulldown = nodep->varType()==AstVarType::TRI0; if (nodep->isPulldown() || nodep->isPullup()) {
bool pullup = nodep->varType()==AstVarType::TRI1;
if (pulldown || pullup) {
AstNode* newp = new AstPull(nodep->fileline(), AstNode* newp = new AstPull(nodep->fileline(),
new AstVarRef(nodep->fileline(), nodep, true), new AstVarRef(nodep->fileline(), nodep, true),
pullup); nodep->isPullup());
m_modp->addStmtp(newp); m_modp->addStmtp(newp);
// We'll iterate on the new AstPull later // We'll iterate on the new AstPull later
} }

24
test_regress/t/t_tri_pull01.v
View File

@ -27,10 +27,14 @@ module t (/*AUTOARG*/
bufif1 (t1, crc[2], cyc[1:0]==2'b10); bufif1 (t1, crc[2], cyc[1:0]==2'b10);
tri t2; tri t2;
t_tri t_tri (.t2, .d(crc[1]), .oe(cyc[1:0]==2'b00)); t_tri2 t_tri2 (.t2, .d(crc[1]), .oe(cyc[1:0]==2'b00));
bufif1 (t2, crc[2], cyc[1:0]==2'b10); bufif1 (t2, crc[2], cyc[1:0]==2'b10);
wire [63:0] result = {55'h0, t2, 3'h0, t1, 3'h0, t0}; tri t3;
t_tri3 t_tri3 (.t3, .d(crc[1]), .oe(cyc[1:0]==2'b00));
bufif1 (t3, crc[2], cyc[1:0]==2'b10);
wire [63:0] result = {51'h0, t3, 3'h0,t2, 3'h0,t1, 3'h0,t0};
// Test loop // Test loop
always @ (posedge clk) begin always @ (posedge clk) begin
@ -54,7 +58,7 @@ module t (/*AUTOARG*/
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop; if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match) // What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hfb06f31a3805822e `define EXPECTED_SUM 64'h04f91df71371e950
if (sum !== `EXPECTED_SUM) $stop; if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
@ -63,7 +67,7 @@ module t (/*AUTOARG*/
endmodule endmodule
module t_tri (/*AUTOARG*/ module t_tri2 (/*AUTOARG*/
// Outputs // Outputs
t2, t2,
// Inputs // Inputs
@ -75,3 +79,15 @@ module t_tri (/*AUTOARG*/
tri1 t2; tri1 t2;
bufif1 (t2, d, oe); bufif1 (t2, d, oe);
endmodule endmodule
module t_tri3 (/*AUTOARG*/
// Outputs
t3,
// Inputs
d, oe
);
output tri1 t3;
input d;
input oe;
bufif1 (t3, d, oe);
endmodule