Tests: Add t_prof test.

test_regress/t/t_prof.pl

@@ -9,7 +9,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 scenarios(vlt_all => 1);
-top_filename("t/t_case_huge.v");
 
 if ($ENV{VERILATOR_TEST_NO_GPROF}) {
     skip("Skipping due to VERILATOR_TEST_NO_GPROF");
@@ -24,9 +23,6 @@ sub dotest {
         verilator_flags2 => ["--stats --prof-cfuncs -CFLAGS '-pg' -LDFLAGS '-pg'"],
         );
 
-    file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 10);
-    file_grep($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i, 10);
-
     unlink $_ foreach (glob "$Self->{obj_dir}/gmon.out.*");
     setenv('GMON_OUT_PREFIX', "$Self->{obj_dir}/gmon.out");
 
@@ -34,8 +30,6 @@ sub dotest {
         check_finished => 1,
         );
 
-    sleep 4;  # Disk flush wait
-
     my $gmon_path;
     $gmon_path = $_ foreach (glob "$Self->{obj_dir}/gmon.out.*");
     $gmon_path or error("Profiler did not create a gmon.out");
@@ -48,6 +42,8 @@ sub dotest {
         check_finished => 0);
 
     file_grep("$Self->{obj_dir}/cfuncs.out", qr/Overall summary by/);
+    file_grep("$Self->{obj_dir}/cfuncs.out", qr/VLib + VL_POWSS_QQQ/);
+    file_grep("$Self->{obj_dir}/cfuncs.out", qr/VBlock + t_prof:/);
 }
 
 1;

test_regress/t/t_prof.v

@@ -0,0 +1,73 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2021 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer cyc=0;
+   wire [63:0] result;
+
+   Test test(/*AUTOINST*/
+             // Outputs
+             .result                    (result[63:0]),
+             // Inputs
+             .clk                       (clk),
+             .cyc                       (cyc));
+
+
+   reg [63:0] sum;
+
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d result=%x\n",$time, cyc, result);
+`endif
+      cyc <= cyc + 1;
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc == 0) begin
+         // Setup
+         sum <= '0;
+      end
+      else if (cyc < 10) begin
+         sum <= '0;
+      end
+      else if (cyc < 90) begin
+      end
+      else if (cyc == 99) begin
+         $write("[%0t] cyc==%0d sum=%x\n",$time, cyc, sum);
+         // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'hfefad16f06ba6b1f
+         if (sum !== `EXPECTED_SUM) $stop;
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule
+
+module Test(/*AUTOARG*/
+   // Outputs
+   result,
+   // Inputs
+   clk, cyc
+   );
+
+   input clk;
+   input int cyc;
+   output reg [63:0] result;
+
+   logic [63:0]      adder;
+
+   always @(posedge clk) begin
+      adder = 0;
+      for (int i = 0; i < 1000; ++i)
+        adder += {32'h0, (cyc+i)} ** 3;
+
+      result <= adder;
+   end
+endmodule