Examples: Cleanup some spacing

examples/json_py/sub.v

@@ -13,6 +13,6 @@ module sub
     );
 
    // Some simple logic
-   always_comb out = ~ in;
+   always_comb out = ~in;
 
 endmodule

examples/make_tracing_c/sub.v

@@ -13,7 +13,7 @@ module sub
 
    // Example counter/flop
    reg [31:0] count_c;
-   always_ff @ (posedge clk) begin
+   always_ff @(posedge clk) begin
       if (!reset_l) begin
          /*AUTORESET*/
          // Beginning of autoreset for uninitialized flops
@@ -32,11 +32,11 @@ module sub
    end
 
    // An example assertion
-   always_ff @ (posedge clk) begin
+   always_ff @(posedge clk) begin
-      AssertionExample: assert (!reset_l || count_c<100);
+      AssertionExample : assert (!reset_l || count_c < 100);
    end
 
    // And example coverage analysis
-   cover property (@(posedge clk) count_c==3);
+   cover property (@(posedge clk) count_c == 3);
 
 endmodule

examples/make_tracing_sc/sub.v

@@ -14,7 +14,7 @@ module sub
 
    // Example counter/flop
    reg [31:0] count_f;
-   always_ff @ (posedge fastclk) begin
+   always_ff @(posedge fastclk) begin
       if (!reset_l) begin
          /*AUTORESET*/
          // Beginning of autoreset for uninitialized flops
@@ -28,7 +28,7 @@ module sub
 
    // Another example flop
    reg [31:0] count_c;
-   always_ff @ (posedge clk) begin
+   always_ff @(posedge clk) begin
       if (!reset_l) begin
          /*AUTORESET*/
          // Beginning of autoreset for uninitialized flops
@@ -38,8 +38,7 @@ module sub
       else begin
          count_c <= count_c + 1;
          if (count_c >= 3) begin
-            $display("[%0t] fastclk is %0d times faster than clk\n",
+            $display("[%0t] fastclk is %0d times faster than clk\n", $time, count_f / count_c);
-                     $time, count_f/count_c);
             // This write is a magic value the Makefile uses to make sure the
             // test completes successfully.
             $write("*-* All Finished *-*\n");
@@ -49,11 +48,11 @@ module sub
    end
 
    // An example assertion
-   always_ff @ (posedge clk) begin
+   always_ff @(posedge clk) begin
-      AssertionExample: assert(!reset_l || count_c<100);
+      AssertionExample : assert (!reset_l || count_c < 100);
    end
 
    // And example coverage analysis
-   cover property (@(posedge clk) count_c==3);
+   cover property (@(posedge clk) count_c == 3);
 
 endmodule

test_regress/t/t_EXAMPLE.v

@@ -45,7 +45,7 @@ module t(/*AUTOARG*/
    wire [63:0] result = {32'h0, out};
 
    // Test loop
-   always @ (posedge clk) begin
+   always @(posedge clk) begin
 `ifdef TEST_VERBOSE
       $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
 `endif