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Allow overriding PERL, YACC, LEX versions.
git-svn-id: file://localhost/svn/verilator/trunk/verilator@794 77ca24e4-aefa-0310-84f0-b9a241c72d87
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7
Changes
@ -3,6 +3,13 @@ Revision history for Verilator
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The contributors that suggested a given feature are shown in []. [by ...]
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indicates the contributor was also the author of the fix; Thanks!
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* Verilator 3.61*
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*** Allow overriding Perl, Flex and Bison versions. [by Robert Farrell]
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**** Default make no longer makes the docs; if you edit the documentation
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sources, run "make info" to get them.
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* Verilator 3.610 09/20/2006
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*** Verilator now works under DJGPP (Pentium GCC). [John Stroebel]
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@ -91,7 +91,7 @@ SUBDIRS = src test_verilated test_c test_sc test_sp test_regress test_vcs
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INFOS = README verilator.txt verilator.html verilator.1 verilator.pdf
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# Files that can be generated, but should be up to date for a distribution.
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DISTDEP = $(INFOS) Makefile
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DISTDEP = info Makefile
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# Files to distribute.
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DISTBIN = $(wildcard bin/verilator-*)
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@ -126,7 +126,7 @@ INST_PROJ_BIN_FILES = \
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DISTFILES := $(DISTFILES_INC)
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all: all_nomsg msg_test
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all_nomsg: verilator_exe info
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all_nomsg: verilator_exe
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.PHONY:verilator_exe
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verilator_exe verilator_bin verilator_bin_dbg:
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@ -218,7 +218,7 @@ installman:
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$(INSTALL_PROGRAM) $$p $(mandir)/man1/$$p; \
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done
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install: all_nomsg info installdirs installbin installman install-msg
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install: all_nomsg installdirs installbin installman install-msg
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install-here: installman ftp
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@ -1575,6 +1575,25 @@ In this example, clk is a bool you can read or set as any other variable.
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The value of normal signals may be set, though clocks shouldn't be changed
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by your code or you'll get strange results.
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=item Should a module be in Verilog or SystemC?
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Sometimes there is a block that just interconnects cells, and have a choice
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as to if you write it in Verilog or SystemC. Everything else being equal,
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best performance is when Verilator sees all of the design. So, look at the
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hierarchy of your design, labeling cells as to if they are SystemC or
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Verilog. Then:
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A module with only SystemC cells below must be SystemC.
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A module with a mix of Verilog and SystemC cells below must be SystemC. (As
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Verilator cannot connect to lower-level SystemC cells.)
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A module with only Verilog cells below can be either, but for best
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performance should be Verilog. (The exception is if you have a design that
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is instantiated many times; in this case Verilating one of the lower
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modules and instantiating that Verilated cells multiple times into a
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SystemC module *may* be faster.)
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=back
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=head1 BUGS
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@ -16,6 +16,8 @@ AC_PROG_CC
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AC_PROG_CXX
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AC_PROG_INSTALL
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AC_PATH_PROG(PERL,perl)
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AC_PATH_PROG(YACC,bison)
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AC_PATH_PROG(LEX,flex)
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dnl Checks for libraries.
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@ -88,7 +88,8 @@ typedef unsigned int vluint32_t; ///< 32-bit unsigned type
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typedef __int64 vlsint64_t; ///< 64-bit signed type
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typedef unsigned __int64 vluint64_t; ///< 64-bit unsigned type
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#else // Linux or compliant Unix flavors, -m64
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# include <stdint.h>
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# include <stdint.h> // Linux and most flavors
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# include <inttypes.h> // Solaris
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typedef uint8_t vluint8_t; ///< 32-bit unsigned type
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typedef uint16_t vluint16_t; ///< 32-bit unsigned type
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typedef int vlsint32_t; ///< 32-bit signed type
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@ -85,3 +85,6 @@ clean mostlyclean distclean maintainer-clean::
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-rm -f *__gen*
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-rm -f *.yy.* y.output y.tab.[cho] *_test
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-rm -f .objcache*
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distclean maintainer-clean::
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-rm -f Makefile Makefile_obj
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@ -48,10 +48,10 @@ COPT = -ggdb -DVL_DEBUG
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endif
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#################
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LEX = flex
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LEX = @LEX@
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LFLAGS = -d
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YACC = bison -y
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YFLAGS = -d -v
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YACC = @YACC@
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YFLAGS = -y -d -v
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#LIBS += -ldl
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#CCMALLOC = /usr/local/lib/ccmalloc-gcc.o -lccmalloc -ldl
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@ -17,6 +17,8 @@ VERILATOR_ROOT := $(shell pwd)/..
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export VERILATOR_ROOT
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PWD := $(shell pwd)
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PERL = perl
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DEBUG_ON = --debug --trace-dups
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#DEBUG = $(DEBUG_ON)
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VALGRIND_ON = $(DEBUG_ON) --gdb "valgrind -v --leak-check=yes"
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@ -31,11 +33,11 @@ VERILATOR_FLAGS = --cc -f $(PWD)/../test_v/input.vc top.v
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#VERILATOR_FLAGS += --trace
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prep:
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perl $(VERILATOR_ROOT)/bin/verilator $(DEBUG) $(VERILATOR_FLAGS)
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$(PERL) $(VERILATOR_ROOT)/bin/verilator $(DEBUG) $(VERILATOR_FLAGS)
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prep_dbg:
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perl $(VERILATOR_ROOT)/bin/verilator $(DEBUG_ON) $(VERILATOR_FLAGS)
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$(PERL) $(VERILATOR_ROOT)/bin/verilator $(DEBUG_ON) $(VERILATOR_FLAGS)
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prep_vg:
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perl $(VERILATOR_ROOT)/bin/verilator $(VALGRIND_ON) $(VERILATOR_FLAGS)
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$(PERL) $(VERILATOR_ROOT)/bin/verilator $(VALGRIND_ON) $(VERILATOR_FLAGS)
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compile:
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cd obj_dir ; $(MAKE) -j 3 -f ../Makefile_obj
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@ -17,6 +17,8 @@ VERILATOR_ROOT := $(shell pwd)/..
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export VERILATOR_ROOT
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PWD := $(shell pwd)
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PERL = perl
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DEBUG_ON = --debug
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######################################################################
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@ -32,11 +34,11 @@ obj_dir/sc_main.cpp: ../test_sp/sc_main.cpp
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cp $^ $@
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prep:
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perl $(VERILATOR_ROOT)/bin/verilator $(VERILATOR_FLAGS)
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$(PERL) $(VERILATOR_ROOT)/bin/verilator $(VERILATOR_FLAGS)
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prep_dbg:
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perl $(VERILATOR_ROOT)/bin/verilator $(DEBUG_ON) $(VERILATOR_FLAGS)
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$(PERL) $(VERILATOR_ROOT)/bin/verilator $(DEBUG_ON) $(VERILATOR_FLAGS)
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prep_dbg_np:
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perl $(VERILATOR_ROOT)/bin/verilator $(DEBUG_ON) $(VERILATOR_FLAGS) --nopublic
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$(PERL) $(VERILATOR_ROOT)/bin/verilator $(DEBUG_ON) $(VERILATOR_FLAGS) --nopublic
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preproc:
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cd obj_dir ; $(MAKE) -j 1 -f ../Makefile_obj preproc
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@ -17,6 +17,8 @@ VERILATOR_ROOT := $(shell pwd)/..
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export VERILATOR_ROOT
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PWD := $(shell pwd)
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PERL = perl
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DEBUG_ON = --debug --trace-dups --output-split 100
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######################################################################
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@ -28,11 +30,11 @@ V_FLAGS = -f $(PWD)/../test_v/input.vc
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VERILATOR_FLAGS = --public --sp --coverage --stats --trace $(V_FLAGS) top.v
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prep:
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perl $(VERILATOR_ROOT)/bin/verilator $(VERILATOR_FLAGS)
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$(PERL) $(VERILATOR_ROOT)/bin/verilator $(VERILATOR_FLAGS)
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prep_dbg:
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perl $(VERILATOR_ROOT)/bin/verilator $(DEBUG_ON) $(VERILATOR_FLAGS)
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$(PERL) $(VERILATOR_ROOT)/bin/verilator $(DEBUG_ON) $(VERILATOR_FLAGS)
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prep_dbg_np:
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perl $(VERILATOR_ROOT)/bin/verilator $(DEBUG_ON) $(VERILATOR_FLAGS) --nopublic
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$(PERL) $(VERILATOR_ROOT)/bin/verilator $(DEBUG_ON) $(VERILATOR_FLAGS) --nopublic
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preproc:
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cd obj_dir ; $(MAKE) -j 1 -f ../Makefile_obj preproc
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