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Internals: Merge VFlag rename. No functional change.

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This commit is contained in:
Wilson Snyder 2012-03-31 11:10:34 -04:00
parent a3ee6131a3
commit 61cbdd1a19
15 changed files with 28 additions and 28 deletions
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4
src/V3Ast.h
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@ -36,8 +36,8 @@
// class V3AstNode;
// Hint class so we can choose constructors
class AstLogicPacked {};
class AstBitPacked {};
class VFlagLogicPacked {};
class VFlagBitPacked {};
//######################################################################

12
src/V3AstNodes.h
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@ -258,11 +258,11 @@ public:
: AstNodeDType(fl) {
init(kwd, signst, 0, NULL);
}
AstBasicDType(FileLine* fl, AstLogicPacked, int wantwidth)
AstBasicDType(FileLine* fl, VFlagLogicPacked, int wantwidth)
: AstNodeDType(fl) {
init(AstBasicDTypeKwd::LOGIC, signedst_NOSIGNED, wantwidth, NULL);
}
AstBasicDType(FileLine* fl, AstBitPacked, int wantwidth)
AstBasicDType(FileLine* fl, VFlagBitPacked, int wantwidth)
: AstNodeDType(fl) {
init(AstBasicDTypeKwd::BIT, signedst_NOSIGNED, wantwidth, NULL);
}
@ -647,20 +647,20 @@ public:
width(dtp->basicp()->width(), 0);
} else width(1, 0);
}
AstVar(FileLine* fl, AstVarType type, const string& name, AstLogicPacked, int wantwidth)
AstVar(FileLine* fl, AstVarType type, const string& name, VFlagLogicPacked, int wantwidth)
:AstNode(fl)
, m_name(name) {
init();
combineType(type);
setOp1p(new AstBasicDType(fl, AstLogicPacked(), wantwidth));
setOp1p(new AstBasicDType(fl, VFlagLogicPacked(), wantwidth));
width(wantwidth,0);
}
AstVar(FileLine* fl, AstVarType type, const string& name, AstBitPacked, int wantwidth)
AstVar(FileLine* fl, AstVarType type, const string& name, VFlagBitPacked, int wantwidth)
:AstNode(fl)
, m_name(name) {
init();
combineType(type);
setOp1p(new AstBasicDType(fl, AstBitPacked(), wantwidth));
setOp1p(new AstBasicDType(fl, VFlagBitPacked(), wantwidth));
width(wantwidth,0);
}
AstVar(FileLine* fl, AstVarType type, const string& name, AstVar* examplep)

4
src/V3Clock.cpp
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@ -85,7 +85,7 @@ private:
AstVar* varp = vscp->varp();
if (!varp->width1()) varp->v3error("Unsupported: Clock edge on non-single bit signal: "<<varp->prettyName());
string newvarname = ((string)"__Vclklast__"+vscp->scopep()->nameDotless()+"__"+varp->shortName());
AstVar* newvarp = new AstVar (vscp->fileline(), AstVarType::MODULETEMP, newvarname, AstLogicPacked(), 1);
AstVar* newvarp = new AstVar (vscp->fileline(), AstVarType::MODULETEMP, newvarname, VFlagLogicPacked(), 1);
m_modp->addStmtp(newvarp);
AstVarScope* newvscp = new AstVarScope(vscp->fileline(), m_scopep, newvarp);
vscp->user1p(newvscp);
@ -103,7 +103,7 @@ private:
AstVarScope* getCreateLocalVar(FileLine* fl, const string& name, AstVar* examplep, int width) {
AstVar* newvarp;
if (width) {
newvarp = new AstVar (fl, AstVarType::BLOCKTEMP, name, AstLogicPacked(), width);
newvarp = new AstVar (fl, AstVarType::BLOCKTEMP, name, VFlagLogicPacked(), width);
} else {
newvarp = new AstVar (fl, AstVarType::BLOCKTEMP, name, examplep); // No range; 1 bit.
}

4
src/V3Const.cpp
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@ -858,9 +858,9 @@ private:
string name1 = ((string)"__Vconcswap"+cvtToStr(m_modp->varNumGetInc()));
string name2 = ((string)"__Vconcswap"+cvtToStr(m_modp->varNumGetInc()));
AstVar* temp1p = new AstVar(sel1p->fileline(), AstVarType::BLOCKTEMP, name1,
AstLogicPacked(), msb1-lsb1+1);
VFlagLogicPacked(), msb1-lsb1+1);
AstVar* temp2p = new AstVar(sel2p->fileline(), AstVarType::BLOCKTEMP, name2,
AstLogicPacked(), msb2-lsb2+1);
VFlagLogicPacked(), msb2-lsb2+1);
m_modp->addStmtp(temp1p);
m_modp->addStmtp(temp2p);
AstNodeAssign* asn1ap=nodep->cloneType

2
src/V3Delayed.cpp
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@ -134,7 +134,7 @@ private:
varp = new AstVar (oldvarscp->fileline(), AstVarType::BLOCKTEMP, name, oldvarscp->varp());
varp->widthSignedFrom(oldvarscp);
} else { // Used for vset and dimensions, so can zero init
varp = new AstVar (oldvarscp->fileline(), AstVarType::BLOCKTEMP, name, AstBitPacked(), width);
varp = new AstVar (oldvarscp->fileline(), AstVarType::BLOCKTEMP, name, VFlagBitPacked(), width);
}
addmodp->addStmtp(varp);
m_modVarMap.insert(make_pair(make_pair(addmodp, name), varp));

2
src/V3Depth.cpp
View File

@ -69,7 +69,7 @@ private:
// though it's one bit wide, needs the mask in the upper bits.
// (Someday we'll have a valid bitmask instead of widths....)
// See t_func_crc for an example test that requires this
AstLogicPacked(), nodep->width());
VFlagLogicPacked(), nodep->width());
if (!m_funcp) nodep->v3fatalSrc("Deep expression not under a function");
m_funcp->addInitsp(varp);
// Replace node tree with reference to var

2
src/V3Link.cpp
View File

@ -198,7 +198,7 @@ private:
}
}
AstVar* newp = new AstVar (forrefp->fileline(), AstVarType::WIRE,
forrefp->name(), AstLogicPacked(), 1);
forrefp->name(), VFlagLogicPacked(), 1);
newp->trace(m_modp->modTrace());
m_modp->addStmtp(newp);

2
src/V3LinkJump.cpp
View File

@ -139,7 +139,7 @@ private:
string name = string("__Vrepeat")+cvtToStr(m_repeatNum++);
// Spec says value is integral, if negative is ignored
AstVar* varp = new AstVar(nodep->fileline(), AstVarType::BLOCKTEMP, name,
AstBitPacked(), 32);
VFlagBitPacked(), 32);
varp->numeric(AstNumeric::SIGNED);
varp->dtypep()->numeric(AstNumeric::SIGNED);
varp->usedLoopIdx(true);

2
src/V3LinkResolve.cpp
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@ -144,7 +144,7 @@ private:
// Make a new temp wire
string newvarname = "__Vsenitemexpr"+cvtToStr(++m_senitemCvtNum);
AstVar* newvarp = new AstVar (sensp->fileline(), AstVarType::MODULETEMP, newvarname,
AstLogicPacked(), 1);
VFlagLogicPacked(), 1);
// We can't just add under the module, because we may be inside a generate, begin, etc.
// We know a SenItem should be under a SenTree/Always etc, we we'll just hunt upwards
AstNode* addwherep = nodep; // Add to this element's next

2
src/V3Premit.cpp
View File

@ -103,7 +103,7 @@ private:
AstVar* getBlockTemp(AstNode* nodep) {
string newvarname = ((string)"__Vtemp"+cvtToStr(m_modp->varNumGetInc()));
AstVar* varp = new AstVar (nodep->fileline(), AstVarType::STMTTEMP, newvarname,
AstLogicPacked(), nodep->widthMin());
VFlagLogicPacked(), nodep->widthMin());
m_funcp->addInitsp(varp);
return varp;
}

6
src/V3Table.cpp
View File

@ -182,7 +182,7 @@ private:
// Index into our table
AstVar* indexVarp = new AstVar (nodep->fileline(), AstVarType::BLOCKTEMP,
"__Vtableidx" + cvtToStr(m_modTables),
AstBitPacked(), m_inWidth);
VFlagBitPacked(), m_inWidth);
m_modp->addStmtp(indexVarp);
AstVarScope* indexVscp = new AstVarScope (indexVarp->fileline(), m_scopep, indexVarp);
m_scopep->addVarp(indexVscp);
@ -191,7 +191,7 @@ private:
FileLine* fl = nodep->fileline();
AstNodeDType* dtypep
= new AstArrayDType (fl,
new AstBasicDType(fl, AstBitPacked(), m_outVarps.size()),
new AstBasicDType(fl, VFlagBitPacked(), m_outVarps.size()),
new AstRange (fl, VL_MASK_I(m_inWidth), 0));
AstVar* chgVarp
= new AstVar (fl, AstVarType::MODULETEMP,
@ -238,7 +238,7 @@ private:
AstNodeDType* dtypep
= new AstArrayDType (fl,
// FUTURE: If support more types, below can use outvarp->dtype()
new AstBasicDType(fl, AstLogicPacked(), outvarp->width()),
new AstBasicDType(fl, VFlagLogicPacked(), outvarp->width()),
new AstRange (fl, VL_MASK_I(m_inWidth), 0));
AstVar* tablevarp
= new AstVar (fl, AstVarType::MODULETEMP,

2
src/V3Trace.cpp
View File

@ -313,7 +313,7 @@ private:
if (!activityNumber) activityNumber++; // For simplicity, always create it
int activityBits = VL_WORDS_I(activityNumber)*VL_WORDSIZE; // For tighter code; round to next 32 bit point.
AstVar* newvarp = new AstVar (m_chgFuncp->fileline(), AstVarType::MODULETEMP,
"__Vm_traceActivity", AstBitPacked(), activityBits);
"__Vm_traceActivity", VFlagBitPacked(), activityBits);
m_topModp->addStmtp(newvarp);
AstVarScope* newvscp = new AstVarScope(newvarp->fileline(), m_highScopep, newvarp);
m_highScopep->addVarp(newvscp);

6
src/V3Tristate.cpp
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@ -233,7 +233,7 @@ private:
AstVar* enp = new AstVar (outrefp->varp()->fileline(),
AstVarType::MODULETEMP,
outrefp->name() + "__en" + suffix + cvtToStr(m_unique++),
AstLogicPacked(), width);
VFlagLogicPacked(), width);
enp->varType2Out();
if (enp->width() != enrhsp->width()) {
@ -412,7 +412,7 @@ private:
AstVar* newlhsp = new AstVar(lhsp->fileline(),
AstVarType::MODULETEMP,
lhsp->name()+"__lhs"+cvtToStr(m_unique++),
AstLogicPacked(), w);
VFlagLogicPacked(), w);
nodep->addStmtp(newlhsp);
// now append this driver to the driver logic.
@ -427,7 +427,7 @@ private:
bitselp = new AstVar(lhsp->fileline(),
AstVarType::MODULETEMP,
lhsp->name()+"__sel"+cvtToStr(m_unique-1),
AstLogicPacked(), ws);
VFlagLogicPacked(), ws);
//
nodep->addStmtp(bitselp);
nodep->addStmtp(new AstAssignW(lhsp->fileline(),

4
src/V3Unknown.cpp
View File

@ -127,7 +127,7 @@ private:
else {
string name = ((string)"__Vlvbound"+cvtToStr(m_modp->varNumGetInc()));
AstVar* varp = new AstVar(fl, AstVarType::MODULETEMP, name,
AstLogicPacked(), prep->width());
VFlagLogicPacked(), prep->width());
m_modp->addStmtp(varp);
AstNode* abovep = prep->backp(); // Grab above point before lose it w/ next replace
@ -288,7 +288,7 @@ private:
+cvtToStr(m_modp->varNumGetInc()));
AstVar* newvarp
= new AstVar (nodep->fileline(), AstVarType::XTEMP, newvarname,
AstLogicPacked(), nodep->width());
VFlagLogicPacked(), nodep->width());
++m_statUnkVars;
AstNRelinker replaceHandle;
nodep->unlinkFrBack(&replaceHandle);

2
src/V3Width.cpp
View File

@ -729,7 +729,7 @@ private:
width=32;
}
if (!nodep->isDouble()) {
AstBasicDType* newp = new AstBasicDType(nodep->fileline(), AstLogicPacked(), width);
AstBasicDType* newp = new AstBasicDType(nodep->fileline(), VFlagLogicPacked(), width);
newp->implicit(true);
newp->numeric(rs); // SIGNED or UNSIGNED
bdtypep->replaceWith(newp);