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Internals: Add some VL_UNLIKELY. No functional change.

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This commit is contained in:
Wilson Snyder 2022-11-29 20:36:56 -05:00
parent b51bb4d0e7
commit 6143892619
3 changed files with 4 additions and 4 deletions
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4
include/verilated.cpp
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@ -2453,7 +2453,7 @@ void VerilatedContext::timeprecision(int value) VL_MT_SAFE {
sc_prec = 15;
}
}
if (value != sc_prec) {
if (VL_UNLIKELY(value != sc_prec)) {
std::ostringstream msg;
msg << "SystemC's sc_set_time_resolution is 10^-" << sc_prec
<< ", which does not match Verilog timeprecision 10^-" << value
@ -2524,7 +2524,7 @@ void VerilatedContext::internalsDump() const VL_MT_SAFE {
void VerilatedContext::addModel(VerilatedModel* modelp) {
threadPoolp(); // Ensure thread pool is created, so m_threads cannot change any more
if (modelp->threads() > m_threads) {
if (VL_UNLIKELY(modelp->threads() > m_threads)) {
std::ostringstream msg;
msg << "VerilatedContext has " << m_threads << " threads but model '"
<< modelp->modelName() << "' (instantiated as '" << modelp->hierName()

2
include/verilated_fst_sc.cpp
View File

@ -29,7 +29,7 @@
//======================================================================
void VerilatedFstSc::open(const char* filename) {
if (!sc_core::sc_get_curr_simcontext()->elaboration_done()) {
if (VL_UNLIKELY(!sc_core::sc_get_curr_simcontext()->elaboration_done())) {
vl_fatal(__FILE__, __LINE__, "VerilatedFstSc",
("%Error: VerilatedFstSc::open(\"" + std::string{filename}
+ "\") is called before sc_core::sc_start(). "

2
include/verilated_vcd_sc.cpp
View File

@ -29,7 +29,7 @@
//======================================================================
void VerilatedVcdSc::open(const char* filename) {
if (!sc_core::sc_get_curr_simcontext()->elaboration_done()) {
if (VL_UNLIKELY(!sc_core::sc_get_curr_simcontext()->elaboration_done())) {
vl_fatal(__FILE__, __LINE__, "VerilatedVcdSc",
("%Error: VerilatedVcdSc::open(\"" + std::string{filename}
+ "\") is called before sc_core::sc_start(). "