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https://github.com/verilator/verilator.git
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Fix isPure to be superset of isOutputter.
This may cause some additional SIDEEFFECT warnings that previously were not shown.
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parent
d5cfe1a379
commit
607c19a67d
@ -801,7 +801,6 @@ AstNode* AstNode::cloneTreeIter(bool needPure) {
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<< this->warnMore()
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<< "... Suggest use a temporary variable in place of this expression");
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// this->v3fatalSrc("cloneTreePure debug backtrace"); // Comment in to debug where caused
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// it
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}
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AstNode* const newp = this->clone();
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if (this->m_op1p) newp->op1p(this->m_op1p->cloneTreeIterList(needPure));
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@ -2786,7 +2786,7 @@ public:
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bool isGateOptimizable() const override { return false; }
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bool isPredictOptimizable() const override { return false; }
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bool isOutputter() override { return true; }
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// but isPure() true
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bool isPure() override { return false; }
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AstCoverDecl* declp() const { return m_declp; } // Where defined
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};
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class AstCoverToggle final : public AstNodeStmt {
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@ -3379,7 +3379,7 @@ public:
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bool isGateOptimizable() const override { return false; }
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bool isPredictOptimizable() const override { return false; }
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bool isOutputter() override { return true; }
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// but isPure() true
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bool isPure() override { return false; }
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AstTraceDecl* declp() const { return m_declp; }
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VTraceType traceType() const { return m_traceType; }
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uint32_t baseCode() const { return m_baseCode; }
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@ -36,9 +36,11 @@ module t
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assign ifs[i].logic_in_intf = data[i];
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end
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endgenerate
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// verilator lint_off SIDEEFFECT
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modify_interface m3 (
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.value(data[return_3()]),
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.intf_inst(ifs[return_3()]));
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// verilator lint_on SIDEEFFECT
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modify_interface m4 (
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.value(data[4]),
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@ -71,9 +71,9 @@ C 'ft/t_wrapper_context.vl22n4pagev_line/topoblockS22,25-29htop0.t
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C 'ft/t_wrapper_context.vl32n4pagev_line/topoblockS32htop0.top' 11
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C 'ft/t_wrapper_context.vl33n7pagev_branch/topoifS33-34htop0.top' 1
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C 'ft/t_wrapper_context.vl33n8pagev_branch/topoelseS36htop0.top' 10
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C 'ft/t_wrapper_context.vl38n4pagev_line/topoblockS38-39htop0.top' 1
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C 'ft/t_wrapper_context.vl38n4pagev_line/topoblockS38-39htop0.top' 34
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C 'ft/t_wrapper_context.vl40n7pagev_branch/topoifS40htop0.top' 0
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C 'ft/t_wrapper_context.vl40n8pagev_branch/topoelseS46htop0.top' 23
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C 'ft/t_wrapper_context.vl40n8pagev_branch/topoelseS46htop0.top' 34
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C 'ft/t_wrapper_context.vl41n11pagev_line/topoelsehtop0.top' 0
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C 'ft/t_wrapper_context.vl47n10pagev_branch/topoifS47-49htop0.top' 1
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C 'ft/t_wrapper_context.vl47n11pagev_branch/topoelsehtop0.top' 33
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@ -71,8 +71,8 @@ C 'ft/t_wrapper_context.vl22n4pagev_line/topoblockS22,25-29htop1.t
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C 'ft/t_wrapper_context.vl32n4pagev_line/topoblockS32htop1.top' 6
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C 'ft/t_wrapper_context.vl33n7pagev_branch/topoifS33-34htop1.top' 1
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C 'ft/t_wrapper_context.vl33n8pagev_branch/topoelseS36htop1.top' 5
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C 'ft/t_wrapper_context.vl38n4pagev_line/topoblockS38-39htop1.top' 1
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C 'ft/t_wrapper_context.vl40n7pagev_branch/topoifS40htop1.top' 13
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C 'ft/t_wrapper_context.vl38n4pagev_line/topoblockS38-39htop1.top' 19
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C 'ft/t_wrapper_context.vl40n7pagev_branch/topoifS40htop1.top' 19
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C 'ft/t_wrapper_context.vl40n8pagev_branch/topoelseS46htop1.top' 0
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C 'ft/t_wrapper_context.vl41n11pagev_line/topoelsehtop1.top' 18
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C 'ft/t_wrapper_context.vl47n10pagev_branch/topoifS47-49htop1.top' 0
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