From 5fce23e90d2a721bb712dc9aacde594558489dda Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 10 Jan 2023 07:18:12 -0500
Subject: [PATCH] Fix empty case items crash (#3851).

---
 Changes                                |  1 +
 src/V3Case.cpp                         |  4 +++-
 test_regress/t/t_case_enum_emptyish.pl | 22 +++++++++++++++++++
 test_regress/t/t_case_enum_emptyish.v  | 29 ++++++++++++++++++++++++++
 4 files changed, 55 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_case_enum_emptyish.pl
 create mode 100644 test_regress/t/t_case_enum_emptyish.v

diff --git a/Changes b/Changes
index 1c9a31b23..42a0560c3 100644
--- a/Changes
+++ b/Changes
@@ -28,6 +28,7 @@ Verilator 5.005 devel
 * Fix self references when param class instantiated (#3833). [Ryszard Rozak, Antmicro Ltd]
 * Fix memory leak in V3Sched, etc. (#3834). [Geza Lore]
 * Fix compatibility with musl libc / Alpine Linux (#3845). [Sören Tempel]
+* Fix empty case items crash (#3851). [rporter]
 
 
 Verilator 5.004 2022-12-14
diff --git a/src/V3Case.cpp b/src/V3Case.cpp
index e643cad88..8a3857c17 100644
--- a/src/V3Case.cpp
+++ b/src/V3Case.cpp
@@ -274,7 +274,9 @@ private:
         // Convert valueItem from AstCaseItem* to the expression
         // Not done earlier, as we may now have a nullptr because it's just a ";" NOP branch
         for (uint32_t i = 0; i < numCases; ++i) {
-            m_valueItem[i] = VN_AS(m_valueItem[i], CaseItem)->stmtsp();
+            if (AstCaseItem* const itemp = VN_AS(m_valueItem[i], CaseItem)) {
+                m_valueItem[i] = itemp->stmtsp();
+            }
         }
         return true;  // All is fine
     }
diff --git a/test_regress/t/t_case_enum_emptyish.pl b/test_regress/t/t_case_enum_emptyish.pl
new file mode 100755
index 000000000..7d49cd2cd
--- /dev/null
+++ b/test_regress/t/t_case_enum_emptyish.pl
@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ["--compiler msvc"],  # We have deep expressions we want to test
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_case_enum_emptyish.v b/test_regress/t/t_case_enum_emptyish.v
new file mode 100644
index 000000000..0dbeb259a
--- /dev/null
+++ b/test_regress/t/t_case_enum_emptyish.v
@@ -0,0 +1,29 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+
+   enum logic [2:0] {
+          e0,
+          e1,
+          e2,
+	  e3
+        } EN;
+
+   initial begin
+
+      unique case (EN)
+        e0 :;
+        e1 :;
+        e2 :;
+        e3 :;
+      endcase
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule