diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 4ed83a2c2..9b9b5fa8d 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -3928,7 +3928,7 @@ class LinkDotResolveVisitor final : public VNVisitor { nodep->refDTypep(defp); nodep->classOrPackagep(foundp->classOrPackagep()); } - } else if (AstClass* const defp = foundp ? VN_AS(foundp->nodep(), Class) : nullptr) { + } else if (AstClass* const defp = foundp ? VN_CAST(foundp->nodep(), Class) : nullptr) { AstPin* const paramsp = nodep->paramsp(); if (paramsp) paramsp->unlinkFrBackWithNext(); AstClassRefDType* const newp @@ -3941,7 +3941,11 @@ class LinkDotResolveVisitor final : public VNVisitor { return; } else { if (foundp) UINFO(1, "Found sym node: " << foundp->nodep() << endl); - nodep->v3error("Can't find typedef: " << nodep->prettyNameQ()); + if (foundp) { + nodep->v3error("Expecting a data type: " << nodep->prettyNameQ()); + } else { + nodep->v3error("Can't find typedef: " << nodep->prettyNameQ()); + } } } iterateChildren(nodep); diff --git a/src/verilog.y b/src/verilog.y index 1be75e85f..52fe7b4bc 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -2137,6 +2137,26 @@ data_type: // ==IEEE: data_type $$ = GRAMMARP->createArray(refp, $4, true); } ; +data_typeAny: // ==IEEE: data_type (accepting idAny) + // // IEEE: data_type_or_incomplete_class_scoped_type parses same as this + // // as can't tell them apart until link + // // This expansion also replicated elsewhere, IE data_type__AndID + data_typeNoRef { $$ = $1; } + // + // // REFERENCES + // + // // IEEE: [ class_scope | package_scope ] type_identifier { packed_dimension } + // // IEEE: class_type + // // IEEE: ps_covergroup_identifier + // // Don't distinguish between types and classes so all these combined + | packageClassScopeE idAny packed_dimensionListE + { AstRefDType* const refp = new AstRefDType{$2, *$2, $1, nullptr}; + $$ = GRAMMARP->createArray(refp, $3, true); } + | packageClassScopeE idAny parameter_value_assignmentClass packed_dimensionListE + { AstRefDType* const refp = new AstRefDType{$2, *$2, $1, $3}; + $$ = GRAMMARP->createArray(refp, $4, true); } + ; + data_typeBasic: // IEEE: part of data_type integer_vector_type signingE rangeListE { $1->setSignedState($2); $$ = GRAMMARP->addRange($1, $3, true); } | integer_atom_type signingE { $1->setSignedState($2); $$ = $1; } @@ -3176,7 +3196,7 @@ type_assignment: // ==IEEE: type_assignment // // note exptOrDataType being a data_type is only for yPARAMETER yTYPE idAny/*new-parameter*/ sigAttrListE { $$ = VARDONEA($1, *$1, nullptr, $2); } - | idAny/*new-parameter*/ sigAttrListE '=' data_type + | idAny/*new-parameter*/ sigAttrListE '=' data_typeAny { $$ = VARDONEA($1, *$1, nullptr, $2); $$->valuep($4); } ; diff --git a/test_regress/t/t_param_type_bad.out b/test_regress/t/t_param_type_bad.out index b2a9ea9de..528bd8fc5 100644 --- a/test_regress/t/t_param_type_bad.out +++ b/test_regress/t/t_param_type_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_param_type_bad.v:9:27: syntax error, unexpected INTEGER NUMBER, expecting TYPE-IDENTIFIER +%Error: t/t_param_type_bad.v:9:27: syntax error, unexpected INTEGER NUMBER, expecting IDENTIFIER or TYPE-IDENTIFIER or randomize 9 | localparam type bad2 = 2; | ^ %Error: Exiting due to diff --git a/test_regress/t/t_param_type_id_bad.out b/test_regress/t/t_param_type_id_bad.out new file mode 100644 index 000000000..4a4d2fb89 --- /dev/null +++ b/test_regress/t/t_param_type_id_bad.out @@ -0,0 +1,4 @@ +%Error: t/t_param_type_id_bad.v:9:34: Expecting a data type: 'i' + 9 | class Cls #(parameter type P_T = i); + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_param_type_id_bad.py b/test_regress/t/t_param_type_id_bad.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_param_type_id_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_param_type_id_bad.v b/test_regress/t/t_param_type_id_bad.v new file mode 100644 index 000000000..fd4482a5f --- /dev/null +++ b/test_regress/t/t_param_type_id_bad.v @@ -0,0 +1,10 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +int i; + +class Cls #(parameter type P_T = i); +endclass diff --git a/test_regress/t/t_no_typedef_bad.out b/test_regress/t/t_typedef_no_bad.out similarity index 51% rename from test_regress/t/t_no_typedef_bad.out rename to test_regress/t/t_typedef_no_bad.out index 8b5c328f7..1d17e5fc6 100644 --- a/test_regress/t/t_no_typedef_bad.out +++ b/test_regress/t/t_typedef_no_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_no_typedef_bad.v:10:4: Can't find typedef: 'sometype' +%Error: t/t_typedef_no_bad.v:10:4: Can't find typedef: 'sometype' 10 | sometype p; | ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_no_typedef_bad.py b/test_regress/t/t_typedef_no_bad.py similarity index 100% rename from test_regress/t/t_no_typedef_bad.py rename to test_regress/t/t_typedef_no_bad.py diff --git a/test_regress/t/t_no_typedef_bad.v b/test_regress/t/t_typedef_no_bad.v similarity index 100% rename from test_regress/t/t_no_typedef_bad.v rename to test_regress/t/t_typedef_no_bad.v