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Associative same variable elimination
git-svn-id: file://localhost/svn/verilator/trunk/verilator@799 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder
parent
94f0809d33
commit
5c93520b27
2
Changes
2
Changes
@ -11,7 +11,7 @@ indicates the contributor was also the author of the fix; Thanks!
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*** Optimize variables set to constants within basic blocks for ~3%.
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**** Default make no longer makes the docs; if you edit the documentation
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**** Default make no longer makes the docs; if you edit the documentation.
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sources, run "make info" to get them.
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**** Optimize additional boolean identities (a|a = a, etc.)
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@ -29,12 +29,12 @@
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// (other items))
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// body
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// Or, converts to a if/else tree.
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// Constants:
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// RHS, Replace 5'bx_1_x with a module global we init to a random value
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// CONST(5'bx_1_x) -> VARREF(_{numberedtemp})
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// -> VAR(_{numberedtemp})
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// -> INITIAL(VARREF(_{numberedtemp}), OR(5'bx_1_x,AND(random,5'b0_1_x))
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// OPTIMIZE: Must not collapse this initial back into the equation.
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// FUTURES:
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// Large 16+ bit tables with constants and no masking (address muxes)
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// Enter all into multimap, sort by value and use a tree of < and == compares.
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// "Diagonal" find of {rightmost,leftmost} bit {set,clear}
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// Ignoring mask, check each value is unique (using multimap as above?)
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// Each branch is then mask-and-compare operation (IE <000000001_000000000 at midpoint.)
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//
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//*************************************************************************
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@ -49,7 +49,8 @@
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#include "V3Ast.h"
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#include "V3Stats.h"
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#define CASE_OVERLAP_WIDTH 12 // Maximum width we can check for overlaps in
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#define CASE_OVERLAP_WIDTH 12 // Maximum width we can check for overlaps in
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#define CASE_BARF 999999 // Magic width when non-constant
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//######################################################################
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@ -126,22 +127,22 @@ private:
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//int debug() { return 9; }
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// METHODS
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bool checkCaseTree(AstCase* nodep) {
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bool isCaseTreeFast(AstCase* nodep) {
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int width = 0;
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m_caseItems = 0;
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m_caseNoOverlapsAllCovered = true;
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for (AstCaseItem* itemp = nodep->itemsp(); itemp; itemp=itemp->nextp()->castCaseItem()) {
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for (AstNode* icondp = itemp->condsp(); icondp!=NULL; icondp=icondp->nextp()) {
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if (icondp->width() > width) width = icondp->width();
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if (!icondp->castConst()) width = 999; // Can't parse; not a constant
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if (!icondp->castConst()) width = CASE_BARF; // Can't parse; not a constant
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m_caseItems++;
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}
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}
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m_caseWidth = width;
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if (width==0 || width > CASE_OVERLAP_WIDTH) {
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m_caseNoOverlapsAllCovered = false;
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return false; // Too wide for analysis
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}
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m_caseWidth = width;
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UINFO(8,"Simple case statement: "<<nodep<<endl);
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// Zero list of items for each value
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for (uint32_t i=0; i<(1UL<<m_caseWidth); i++) m_valueItem[i] = NULL;
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@ -172,7 +173,7 @@ private:
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}
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}
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// Defaults were moved to last in the caseitem list by V3Link
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if (!itemp->condsp()) { // Case statement's default... Fill the table
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if (itemp->isDefault()) { // Case statement's default... Fill the table
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for (uint32_t i=0; i<(1UL<<m_caseWidth); i++) {
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if (!m_valueItem[i]) m_valueItem[i] = itemp;
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}
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@ -207,7 +208,7 @@ private:
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AstNode* tree1p = replaceCaseFastRecurse(cexprp, msb-1, upperValue | (1UL<<msb));
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if (tree0p == tree1p) {
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// Same logic on both sides, so we can just return one of em
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// Same logic on both sides, so we can just return one of 'em
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return tree0p;
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}
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// We could have a "checkerboard" with A B A B, we can use the same IF on both edges
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@ -357,7 +358,7 @@ private:
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V3Case::caseLint(nodep);
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nodep->iterateChildren(*this);
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if (debug()>=9) nodep->dumpTree(cout," case_old: ");
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if (checkCaseTree(nodep) && v3Global.opt.oCase()) {
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if (isCaseTreeFast(nodep) && v3Global.opt.oCase()) {
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// It's a simple priority encoder or complete statement
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// we can make a tree of statements to avoid extra comparisons
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m_statCaseFast++;
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@ -381,7 +382,7 @@ public:
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}
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virtual ~CaseVisitor() {
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V3Stats::addStat("Optimizations, Cases parallelized", m_statCaseFast);
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V3Stats::addStat("Optimizations, Cases priority-encoded", m_statCaseSlow);
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V3Stats::addStat("Optimizations, Cases complex", m_statCaseSlow);
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}
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};
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@ -70,6 +70,16 @@ private:
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if (!rnodep->lhsp()->castConst()) return false;
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return true;
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}
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bool operandAsvSame (AstNode* nodep) {
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// BIASV(SAMEa, BIASV(SAMEb,...)) -> BIASV( BIASV(SAMEa,SAMEb), ...)
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AstNodeBiComAsv* bnodep = nodep->castNodeBiComAsv();
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if (!bnodep) return false;
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AstNodeBiComAsv* rnodep = bnodep->rhsp()->castNodeBiComAsv();
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if (!rnodep) return false;
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if (rnodep->type() != bnodep->type()) return false;
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if (rnodep->width() != bnodep->width()) return false;
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return operandsSame(bnodep->lhsp(), rnodep->lhsp());
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}
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bool operandHugeShiftL(AstNodeBiop* nodep) {
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return (nodep->rhsp()->castConst()
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&& nodep->rhsp()->castConst()->asInt() >= (uint32_t)(nodep->width()));
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@ -284,8 +294,9 @@ private:
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// Keep RHS, remove LHS
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replaceWChild(nodep, nodep->rhsp());
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}
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void replaceAsvConst (AstNodeBiop* nodep) {
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void replaceAsv (AstNodeBiop* nodep) {
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// BIASV(CONSTa, BIASV(CONSTb, c)) -> BIASV( BIASV_CONSTED(a,b), c)
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// BIASV(SAMEa, BIASV(SAMEb, c)) -> BIASV( BIASV(SAMEa,SAMEb), c)
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//nodep->dumpTree(cout, " repAsvConst_old: ");
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AstNode* ap = nodep->lhsp();
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AstNodeBiop* rp = nodep->rhsp()->castNodeBiop();
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@ -299,7 +310,7 @@ private:
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nodep->rhsp(cp);
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rp->lhsp(ap);
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rp->rhsp(bp);
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replaceConst(rp);
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if (rp->lhsp()->castConst() && rp->rhsp()->castConst()) replaceConst(rp);
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//nodep->dumpTree(cout, " repAsvConst_new: ");
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}
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void replaceExtend (AstNode* nodep, AstNode* arg0p) {
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@ -1017,8 +1028,9 @@ private:
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TREEOP("AstNodeCond{$condp.width1, $expr1p.width1, $expr1p.isZero, $expr2p}", "AstAnd{AstNot{$condp}, $expr2p}"); // a?0:b == ~a&b
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TREEOP("AstNodeCond{!$condp.width1, operandBoolShift(nodep->condp())}", "replaceBoolShift(nodep->condp())");
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// Prefer constants on left, since that often needs a shift, it lets constant red remove the shift
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TREEOP("AstNodeBiCom{$lhsp, $rhsp.castConst}", "swapSides(nodep)");
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TREEOP("AstNodeBiComAsv{operandAsvConst(nodep)}", "replaceAsvConst(nodep)");
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TREEOP("AstNodeBiCom{!$lhsp.castConst, $rhsp.castConst}", "swapSides(nodep)");
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TREEOP("AstNodeBiComAsv{operandAsvConst(nodep)}", "replaceAsv(nodep)");
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TREEOP("AstNodeBiComAsv{operandAsvSame(nodep)}", "replaceAsv(nodep)");
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// v--- *1* as These ops are always first, as we warn before replacing
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TREEOP1("AstLt {$lhsp, $rhsp.isZero}", "replaceNumSigned(nodep,0)");
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TREEOP1("AstGte {$lhsp, $rhsp.isZero}", "replaceNumSigned(nodep,1)");
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@ -1067,6 +1079,7 @@ private:
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// AstLogAnd/AstLogOr already converted to AstAnd/AstOr for these rules
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// AstAdd->ShiftL(#,1) but uncommon
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TREEOP("AstAnd {operandsSame($lhsp,,$rhsp)}", "replaceWLhs(nodep)");
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TREEOP("AstChangeXor{operandsSame($lhsp,,$rhsp)}", "replaceZero(nodep)");
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TREEOP("AstDiv {operandsSame($lhsp,,$rhsp)}", "replaceNum(nodep,1)");
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TREEOP("AstDivS {operandsSame($lhsp,,$rhsp)}", "replaceNum(nodep,1)");
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TREEOP("AstOr {operandsSame($lhsp,,$rhsp)}", "replaceWLhs(nodep)");
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@ -1085,6 +1098,8 @@ private:
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TREEOP("AstLteS {operandsSame($lhsp,,$rhsp)}", "replaceNum(nodep,1)");
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TREEOP("AstNeq {operandsSame($lhsp,,$rhsp)}", "replaceZero(nodep)");
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TREEOP("AstNeqCase{operandsSame($lhsp,,$rhsp)}", "replaceZero(nodep)");
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TREEOP("AstLogAnd {operandsSame($lhsp,,$rhsp), $lhsp.width1}", "replaceWLhs(nodep)");
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TREEOP("AstLogOr {operandsSame($lhsp,,$rhsp), $lhsp.width1}", "replaceWLhs(nodep)");
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///=== Verilog operators
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// Comparison against 1'b0/1'b1; must be careful about widths.
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// These use Not, so must be Verilog only
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@ -115,9 +115,7 @@ V3Number::V3Number (FileLine* fileline, const char* sourcep) {
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// Otherwise...
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else if (!m_sized) {
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width(32, false); // Says the spec.
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#ifndef VL_UNSIGNED
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if (unbased) isSigned(true); // Also says the spec.
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#endif
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}
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// Ignore leading blanks
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@ -284,9 +284,7 @@ private:
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// VISITORS - defaults
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virtual void visit(AstNodeMath* nodep, AstNUser*) {
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#ifndef VL_UNSIGNED
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nodep->v3fatalSrc("Visit function missing? Signedness unknown for this node: "<<nodep);
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#endif
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nodep->iterateChildren(*this);
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}
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virtual void visit(AstNode* nodep, AstNUser*) {
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@ -347,12 +345,6 @@ public:
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class SignedRemoveVisitor : public AstNVisitor {
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private:
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// METHODS
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void supportCheck(AstNode* nodep) {
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#ifdef VL_UNSIGNED
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if (nodep->isSigned()) nodep->v3error("Unsupported: signed numbers");
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#endif
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}
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// VISITORS
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virtual void visit(AstSigned* nodep, AstNUser*) {
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replaceWithSignedVersion(nodep, nodep->lhsp()->unlinkFrBack()); nodep=NULL;
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@ -362,13 +354,11 @@ private:
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}
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virtual void visit(AstNode* nodep, AstNUser*) {
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nodep->iterateChildren(*this);
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supportCheck(nodep);
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}
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void replaceWithSignedVersion(AstNode* nodep, AstNode* newp) {
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UINFO(6," Replace "<<nodep<<" w/ "<<newp<<endl);
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nodep->replaceWith(newp);
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newp->widthSignedFrom(nodep);
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supportCheck(nodep);
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pushDeletep(nodep); nodep=NULL;
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}
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public:
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@ -1086,9 +1086,7 @@ AstVar* V3Parse::createVariable(FileLine* fileline, string name, AstRange* array
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rangep->cloneTree(false),
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arrayp);
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nodep->isSigned(V3Parse::s_varSigned);
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#ifndef VL_UNSIGNED
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if (type == AstVarType::INTEGER) nodep->isSigned(true);
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#endif
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if (V3Parse::s_varDecl != AstVarType::UNKNOWN) nodep->combineType(V3Parse::s_varDecl);
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if (V3Parse::s_varIO != AstVarType::UNKNOWN) nodep->combineType(V3Parse::s_varIO);
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18
test_regress/t/t_case_wild.pl
Executable file
18
test_regress/t/t_case_wild.pl
Executable file
@ -0,0 +1,18 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
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# $Id$
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# General Public License or the Perl Artistic License.
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compile (
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);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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93
test_regress/t/t_case_wild.v
Normal file
93
test_regress/t/t_case_wild.v
Normal file
@ -0,0 +1,93 @@
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// $Id$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2006 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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reg out1;
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reg [4:0] out2;
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sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
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always @ (posedge clk) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x out=%x,%x\n",$time, cyc, crc, sum, out1,out2);
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
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if (cyc==0) begin
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// Setup
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crc <= 64'h00000000_00000097;
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sum <= 64'h0;
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end
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else if (cyc==90) begin
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if (sum != 64'hf0afc2bfa78277c5) $stop;
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end
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else if (cyc==91) begin
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end
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else if (cyc==92) begin
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end
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else if (cyc==93) begin
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end
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else if (cyc==94) begin
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end
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else if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module sub (/*AUTOARG*/
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// Outputs
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out1, out2,
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// Inputs
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in
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);
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input [23:0] in;
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output reg out1;
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output reg [4:0] out2;
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always @* begin
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casez (in)
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24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00};
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24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00};
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24'b????_????_????_????_????_??10 : {out1,out2} = {1'b1,5'h01};
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24'b????_????_????_????_????_?100 : {out1,out2} = {1'b1,5'h02};
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24'b????_????_????_????_????_1000 : {out1,out2} = {1'b1,5'h03};
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24'b????_????_????_????_???1_0000 : {out1,out2} = {1'b1,5'h04};
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24'b????_????_????_????_??10_0000 : {out1,out2} = {1'b1,5'h05};
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24'b????_????_????_????_?100_0000 : {out1,out2} = {1'b1,5'h06};
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24'b????_????_????_????_1000_0000 : {out1,out2} = {1'b1,5'h07};
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// Same pattern, but reversed to test we work OK.
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24'b1000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h17};
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24'b?100_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h16};
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24'b??10_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h15};
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24'b???1_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h14};
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24'b????_1000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h13};
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24'b????_?100_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h12};
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24'b????_??10_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h11};
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24'b????_???1_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h10};
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24'b????_????_1000_0000_0000_0000 : {out1,out2} = {1'b1,5'h0f};
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24'b????_????_?100_0000_0000_0000 : {out1,out2} = {1'b1,5'h0e};
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24'b????_????_??10_0000_0000_0000 : {out1,out2} = {1'b1,5'h0d};
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24'b????_????_???1_0000_0000_0000 : {out1,out2} = {1'b1,5'h0c};
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24'b????_????_????_1000_0000_0000 : {out1,out2} = {1'b1,5'h0b};
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24'b????_????_????_?100_0000_0000 : {out1,out2} = {1'b1,5'h0a};
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24'b????_????_????_??10_0000_0000 : {out1,out2} = {1'b1,5'h09};
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24'b????_????_????_???1_0000_0000 : {out1,out2} = {1'b1,5'h08};
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endcase
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end
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endmodule
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@ -54,7 +54,7 @@ our $Raise_Weight_Max = 50;
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'VCONST'=> {weight=>1&&20, width=>0, sc=>1, terminal=>1, v=>'%v', },
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'VIDNEW'=> {weight=>1&&10, width=>0, sc=>1, terminal=>0, v=>'%i', },
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'VIDOLD'=> {weight=>1&&20, width=>0, sc=>1, terminal=>0, v=>'%i', },
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'VIDSAME'=> {weight=>1&&200, width=>0, sc=>1, terminal=>0, v=>'%i', },
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'VIDSAME'=> {weight=>1&&20, width=>0, sc=>1, terminal=>0, v=>'%i', },
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'VRANGE'=> {weight=>1&&30, width=>0, signed=>0,sc=>0, terminal=>0, v=>'%i[%2:%3]', },
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'VBITSEL'=> {weight=>1&&10, width=>1, signed=>0,sc=>0, terminal=>0, v=>'%i[%2]', },
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'VBITSELP'=> {weight=>1&&10, width=>0, signed=>0,sc=>0, terminal=>0, v=>'%i[%2+:%3]', },
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