From 5c923d6629030a41119b94a5802b119a48327529 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 28 Sep 2024 17:58:26 -0400 Subject: [PATCH] Fix to avoid IMPLICIT creation if data type of same name. --- src/V3LinkDot.cpp | 8 ++++---- test_regress/t/t_lint_implicit_func_bad.out | 4 ++++ test_regress/t/t_lint_implicit_func_bad.py | 18 ++++++++++++++++++ test_regress/t/t_lint_implicit_func_bad.v | 13 +++++++++++++ test_regress/t/t_lint_implicit_type_bad.out | 4 ++++ test_regress/t/t_lint_implicit_type_bad.py | 18 ++++++++++++++++++ test_regress/t/t_lint_implicit_type_bad.v | 12 ++++++++++++ 7 files changed, 73 insertions(+), 4 deletions(-) create mode 100644 test_regress/t/t_lint_implicit_func_bad.out create mode 100755 test_regress/t/t_lint_implicit_func_bad.py create mode 100644 test_regress/t/t_lint_implicit_func_bad.v create mode 100644 test_regress/t/t_lint_implicit_type_bad.out create mode 100755 test_regress/t/t_lint_implicit_type_bad.py create mode 100644 test_regress/t/t_lint_implicit_type_bad.v diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 8ecd3ca35..140e71ec1 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -3050,8 +3050,7 @@ class LinkDotResolveVisitor final : public VNVisitor { m_ds.m_dotPos = DP_MEMBER; } else { // Cells/interfaces can't be implicit - const bool isCell = foundp ? VN_IS(foundp->nodep(), Cell) : false; - const bool checkImplicit = (!m_ds.m_dotp && m_ds.m_dotText == "" && !isCell); + const bool checkImplicit = (!m_ds.m_dotp && m_ds.m_dotText == "" && !foundp); const bool err = !(checkImplicit && m_statep->implicitOk(m_modp, nodep->name())); if (err) { @@ -3086,7 +3085,8 @@ class LinkDotResolveVisitor final : public VNVisitor { if (checkImplicit) { // Create if implicit, and also if error (so only complain once) // Else if a scope is allowed, making a signal won't help error cascade - auto varp = createImplicitVar(m_curSymp, nodep, m_modp, m_modSymp, err); + AstVar* const varp + = createImplicitVar(m_curSymp, nodep, m_modp, m_modSymp, err); AstVarRef* const newp = new AstVarRef{nodep->fileline(), varp, VAccess::READ}; nodep->replaceWith(newp); @@ -4133,7 +4133,7 @@ void V3LinkDot::linkDotGuts(AstNetlist* rootp, VLinkDotStep step) { v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("prelinkdot-find.tree")); } if (step == LDS_PRIMARY || step == LDS_PARAMED) { - // Initial link stage, resolve parameters + // Initial link stage, resolve parameters and interfaces const LinkDotParamVisitor visitors{rootp, &state}; if (dumpTreeEitherLevel() >= 9) { V3Global::dumpCheckGlobalTree("prelinkdot-param"); diff --git a/test_regress/t/t_lint_implicit_func_bad.out b/test_regress/t/t_lint_implicit_func_bad.out new file mode 100644 index 000000000..6d790a04c --- /dev/null +++ b/test_regress/t/t_lint_implicit_func_bad.out @@ -0,0 +1,4 @@ +%Error: t/t_lint_implicit_func_bad.v:12:11: Illegal call of a task as a function: 'imp_func_conflict' + 12 | assign imp_func_conflict = 1'b1; + | ^~~~~~~~~~~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_lint_implicit_func_bad.py b/test_regress/t/t_lint_implicit_func_bad.py new file mode 100755 index 000000000..c0608225e --- /dev/null +++ b/test_regress/t/t_lint_implicit_func_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_implicit_func_bad.v b/test_regress/t/t_lint_implicit_func_bad.v new file mode 100644 index 000000000..2d3dbe2fb --- /dev/null +++ b/test_regress/t/t_lint_implicit_func_bad.v @@ -0,0 +1,13 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + function void imp_func_conflict(); + endfunction + +`default_nettype wire + assign imp_func_conflict = 1'b1; +endmodule diff --git a/test_regress/t/t_lint_implicit_type_bad.out b/test_regress/t/t_lint_implicit_type_bad.out new file mode 100644 index 000000000..8f0e6e645 --- /dev/null +++ b/test_regress/t/t_lint_implicit_type_bad.out @@ -0,0 +1,4 @@ +%Error: t/t_lint_implicit_type_bad.v:11:11: syntax error, unexpected TYPE-IDENTIFIER + 11 | assign imp_type_conflict = 1'b1; + | ^~~~~~~~~~~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_lint_implicit_type_bad.py b/test_regress/t/t_lint_implicit_type_bad.py new file mode 100755 index 000000000..c0608225e --- /dev/null +++ b/test_regress/t/t_lint_implicit_type_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_implicit_type_bad.v b/test_regress/t/t_lint_implicit_type_bad.v new file mode 100644 index 000000000..24a373808 --- /dev/null +++ b/test_regress/t/t_lint_implicit_type_bad.v @@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + typedef int imp_type_conflict; + +`default_nettype wire + assign imp_type_conflict = 1'b1; +endmodule