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https://github.com/verilator/verilator.git
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Support empty queue as dynarray default value (#5055)
Signed-off-by: Arkadiusz Kozdra <akozdra@antmicro.com>
This commit is contained in:
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@ -1839,10 +1839,13 @@ AstNodeFTask* V3Task::taskConnectWrapNew(AstNodeFTask* taskp, const string& newn
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newPortp->funcLocal(true);
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newPortp->funcLocal(true);
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newTaskp->addStmtsp(newPortp);
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newTaskp->addStmtsp(newPortp);
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// Runtime-assign it to the default
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// Runtime-assign it to the default
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AstAssign* const newAssignp = new AstAssign{
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if (!VN_IS(valuep, EmptyQueue)) {
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valuep->fileline(), new AstVarRef{valuep->fileline(), newPortp, VAccess::WRITE},
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AstAssign* const newAssignp
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valuep->cloneTree(true)};
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= new AstAssign{valuep->fileline(),
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newTaskp->addStmtsp(newAssignp);
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new AstVarRef{valuep->fileline(), newPortp, VAccess::WRITE},
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valuep->cloneTree(true)};
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newTaskp->addStmtsp(newAssignp);
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}
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}
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}
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oldNewVars.emplace(portp, newPortp);
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oldNewVars.emplace(portp, newPortp);
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const VAccess pinAccess = portp->isWritable() ? VAccess::WRITE : VAccess::READ;
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const VAccess pinAccess = portp->isWritable() ? VAccess::WRITE : VAccess::READ;
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@ -1228,7 +1228,7 @@ class WidthVisitor final : public VNVisitor {
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}
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}
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void visit(AstEmptyQueue* nodep) override {
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void visit(AstEmptyQueue* nodep) override {
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nodep->dtypeSetEmptyQueue();
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nodep->dtypeSetEmptyQueue();
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if (!VN_IS(nodep->backp(), Assign)) {
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if (!VN_IS(nodep->backp(), Assign) && !VN_IS(nodep->backp(), Var)) {
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nodep->v3warn(E_UNSUPPORTED,
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nodep->v3warn(E_UNSUPPORTED,
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"Unsupported/Illegal: empty queue ('{}') in this context");
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"Unsupported/Illegal: empty queue ('{}') in this context");
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}
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}
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@ -4888,7 +4888,8 @@ class WidthVisitor final : public VNVisitor {
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}
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}
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if (VN_IS(nodep->rhsp(), EmptyQueue)) {
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if (VN_IS(nodep->rhsp(), EmptyQueue)) {
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UINFO(9, "= {} -> .delete(): " << nodep);
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UINFO(9, "= {} -> .delete(): " << nodep);
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if (!VN_IS(nodep->lhsp()->dtypep()->skipRefp(), QueueDType)) {
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const AstNodeDType* const lhsDtp = nodep->lhsp()->dtypep()->skipRefp();
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if (!VN_IS(lhsDtp, QueueDType) && !VN_IS(lhsDtp, DynArrayDType)) {
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nodep->v3warn(E_UNSUPPORTED,
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nodep->v3warn(E_UNSUPPORTED,
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"Unsupported/Illegal: empty queue ('{}') in this assign context");
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"Unsupported/Illegal: empty queue ('{}') in this assign context");
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VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
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VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
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@ -13,6 +13,7 @@ module t (/*AUTOARG*/);
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int a2[] = {14, 15};
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int a2[] = {14, 15};
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int a3[] = '{16};
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int a3[] = '{16};
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int a4[] = {17};
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int a4[] = {17};
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int a5[] = {};
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initial begin
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initial begin
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`checkh(a1.size, 2);
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`checkh(a1.size, 2);
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@ -29,6 +30,8 @@ module t (/*AUTOARG*/);
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`checkh(a4.size, 1);
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`checkh(a4.size, 1);
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`checkh(a4[0], 17);
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`checkh(a4[0], 17);
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`checkh(a5.size, 0);
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$write("*-* All Finished *-*\n");
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$write("*-* All Finished *-*\n");
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$finish;
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$finish;
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end
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end
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21
test_regress/t/t_queue_empty_pin.pl
Executable file
21
test_regress/t/t_queue_empty_pin.pl
Executable file
@ -0,0 +1,21 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2022 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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18
test_regress/t/t_queue_empty_pin.v
Normal file
18
test_regress/t/t_queue_empty_pin.v
Normal file
@ -0,0 +1,18 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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task tsk(int q[] = {});
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if (q.size != 0) $stop;
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endtask
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initial begin
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tsk();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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